2001 |
53 | EE | Yasuhiko Takenaga,
Kouji Nakajima,
Shuzo Yajima:
Tree-shellability of Boolean functions.
Theor. Comput. Sci. 262(1): 633-647 (2001) |
2000 |
52 | | Yasuhiko Takenaga,
Shuzo Yajima:
Hardness of identifying the minimum ordered binary decision diagram.
Discrete Applied Mathematics 107(1-3): 191-201 (2000) |
1998 |
51 | EE | Kazuo Iwama,
Mitsushi Nouzoe,
Shuzo Yajima:
Optimizing OBDDs Is Still Intractable for Monotone Functions.
MFCS 1998: 625-635 |
1997 |
50 | | Yasuhiko Takenaga,
Mitsushi Nouzoe,
Shuzo Yajima:
Size and Variable Ordering of OBDDs Representing Treshold Functions.
COCOON 1997: 91-100 |
49 | | Takashi Horiyama,
Shuzo Yajima:
Exponential Lower Bounds on the Size of OBDDs Representing Integer Divistion.
ISAAC 1997: 163-172 |
48 | | Massayuki Ito,
Naofumi Takagi,
Shuzo Yajima:
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.
IEEE Trans. Computers 46(4): 495-498 (1997) |
47 | | Takafumi Hamano,
Naofumi Takagi,
Shuzo Yajima,
Franco P. Preparata:
O(n)-Depth Modular Exponentiation Circuit Algorithm.
IEEE Trans. Computers 46(6): 701-704 (1997) |
46 | EE | Kazuhisa Hosaka,
Yasuhiko Takenaga,
T. Kaneda,
Shuzo Yajima:
Size of Ordered Binary Decision Diagrams Representing Threshold Functions.
Theor. Comput. Sci. 180(1-2): 47-60 (1997) |
1996 |
45 | EE | Masayuki Ito,
Naofumi Takagi,
Shuzo Yajima:
Square Rooting by Iterative Multiply-Additions.
Inf. Process. Lett. 60(5): 267-269 (1996) |
1995 |
44 | EE | Kiyoharu Hamaguchi,
Akihito Morita,
Shuzo Yajima:
Efficient construction of binary moment diagrams for verifying arithmetic circuits.
ICCAD 1995: 78-82 |
43 | EE | Takafumi Hamano,
Naofumi Takagi,
Shuzo Yajima,
Franco P. Preparata:
O(n)-depth circuit algorithm for modular exponentiation.
IEEE Symposium on Computer Arithmetic 1995: 188-192 |
42 | EE | Masayuki Ito,
Naofumi Takagi,
Shuzo Yajima:
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.
IEEE Symposium on Computer Arithmetic 1995: 2-8 |
1994 |
41 | | Kazuhisa Hosaka,
Yasuhiko Takenaga,
Shuzo Yajima:
On the Size of Ordered Binary Decision Diagrams Representing Threshold Functions.
ISAAC 1994: 584-592 |
40 | EE | Noriyuki Takahashi,
Nagisa Ishiura,
Shuzo Yajima:
Fault simulation for multiple faults by Boolean function manipulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 531-535 (1994) |
1993 |
39 | EE | Hiroyuki Ochi,
Koichi Yasuoka,
Shuzo Yajima:
Breadth-first manipulation of very large binary-decision diagrams.
ICCAD 1993: 48-55 |
38 | | Seiichiro Tani,
Kiyoharu Hamaguchi,
Shuzo Yajima:
The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams.
ISAAC 1993: 389-398 |
1992 |
37 | | Kiyoharu Hamaguchi,
Hiromi Hiraishi,
Shuzo Yajima:
Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic.
CAV 1992: 206-219 |
36 | | Naofumi Takagi,
Shuzo Yajima:
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem.
IEEE Trans. Computers 41(7): 887-891 (1992) |
35 | | Kiyoharu Hamaguchi,
Hiromi Hiraishi,
Shuzo Yajima:
Infinity-Regular Temporal Logic and its Model Checking Problem.
Theor. Comput. Sci. 103(2): 191-204 (1992) |
1991 |
34 | | Hiromi Hiraishi,
Kiyoharu Hamaguchi,
Hiroyuki Ochi,
Shuzo Yajima:
Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification.
CAV 1991: 214-224 |
33 | | Kiyoharu Hamaguchi,
Hiromi Hiraishi,
Shuzo Yajima:
Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic.
CAV 1991: 410-420 |
32 | EE | Hiroyuki Ochi,
Nagisa Ishiura,
Shuzo Yajima:
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing.
DAC 1991: 413-416 |
31 | EE | Yutaka Deguchi,
Nagisa Ishiura,
Shuzo Yajima:
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits.
DAC 1991: 650-655 |
30 | | Nagisa Ishiura,
Hiroshi Sawada,
Shuzo Yajima:
Minimazation of Binary Decision Diagrams Based on Exchanges of Variables.
ICCAD 1991: 472-475 |
29 | | Noriyuki Takahashi,
Nagisa Ishiura,
Shuzo Yajima:
Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets.
ICCAD 1991: 550-553 |
28 | | Naofumi Takagi,
Tohru Asada,
Shuzo Yajima:
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation.
IEEE Trans. Computers 40(9): 989-995 (1991) |
1990 |
27 | | Kiyoharu Hamaguchi,
Hiromi Hiraishi,
Shuzo Yajima:
Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity.
CAV 1990: 253-262 |
26 | EE | Nagisa Ishiura,
Yutaka Deguchi,
Shuzo Yajima:
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram.
DAC 1990: 130-135 |
25 | EE | Shin-ichi Minato,
Nagisa Ishiura,
Shuzo Yajima:
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation.
DAC 1990: 52-57 |
24 | EE | Nagisa Ishiura,
Hiroto Yasuura,
Shuzo Yajima:
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I.
DAC 1990: 8-13 |
23 | EE | Nagisa Ishiura,
Masyuki Ito,
Shuzo Yajima:
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(8): 868-875 (1990) |
1989 |
22 | EE | Nagisa Ishiura,
M. Takahashi,
Shuzo Yajima:
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits.
DAC 1989: 497-502 |
1988 |
21 | | Yasuo Okabe,
Shuzo Yajima:
Parallel Computational Complexity of Logic Programs and Alternating Turing Machines.
FGCS 1988: 356-363 |
1987 |
20 | | Naofumi Takagi,
Shuzo Yajima:
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic.
IEEE Trans. Computers 36(11): 1310-1317 (1987) |
19 | EE | Nagisa Ishiura,
Hiroto Yasuura,
Shuzo Yajima:
High-Speed Logic Simulation on Vector Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(3): 305-321 (1987) |
1985 |
18 | | Naofumi Takagi,
Hiroto Yasuura,
Shuzo Yajima:
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
IEEE Trans. Computers 34(9): 789-796 (1985) |
1984 |
17 | | Hiroto Yasuura,
Shuzo Yajima:
Hardware Algorithms for VLSI Systems.
VLSI Engineering 1984: 105-129 |
1982 |
16 | | Shuzo Yajima,
Hiroto Yasuura:
Hardware Algorithms and Logic Design Automation. An Overview and Progress Report.
RIMS Symposium on Software Science and Engineering 1982: 147-164 |
15 | EE | Yahiko Kambayashi,
Masatoshi Yoshikawa,
Shuzo Yajima:
Query Processing for Distributed Databases Using Generalized Semi-Joins.
SIGMOD Conference 1982: 151-160 |
14 | | Narao Nakatsu,
Yahiko Kambayashi,
Shuzo Yajima:
A Longest Common Subsequence Algorithm Suitable for Similar Text Strings.
Acta Inf. 18: 171-179 (1982) |
13 | | Hiroto Yasuura,
Naofumi Takagi,
Shuzo Yajima:
The Parallel Enumeration Sorting Scheme for VLSI.
IEEE Trans. Computers 31(12): 1192-1201 (1982) |
1981 |
12 | EE | Yahiko Kambayashi,
Narao Nakatsu,
Shuzo Yajima:
Data compression procedures utilizing the similarity of data.
AFIPS National Computer Conference 1981: 555-562 |
11 | EE | Yahiko Kambayashi,
Takaki Hayashi,
Shuzo Yajima:
Dynamic Clustering Procedures for Bibliographic Data.
SIGIR 1981: 90-99 |
1979 |
10 | | Katsumi Tanaka,
Yahiko Kambayashi,
Shuzo Yajima:
Organization of quasi-consecutive retrieval files.
Inf. Syst. 4(3): 23-33 (1979) |
1978 |
9 | | Yahiko Kambayashi,
Katsumi Tanaka,
Shuzo Yajima:
Problems of Relational Database Design.
Data Base Design Techniques I 1978: 172-218 |
8 | | Katsumi Tanaka,
Chung Le Viet,
Yahiko Kambayashi,
Shuzo Yajima:
A file organization suitable for relational database operations.
Mathematical Studies of Information Processing 1978: 193-227 |
7 | | Yahiko Kambayashi,
Takaki Hayashi,
Y. Tanaka,
Shuzo Yajima:
A Linear Storage Space Algorithm for a Reference Structure Index.
Inf. Process. Lett. 7(2): 66-71 (1978) |
1977 |
6 | EE | Yahiko Kambayashi,
Katsumi Tanaka,
Shuzo Yajima:
A Relational Data Language with Simplified Binary Relation Handling Capability.
VLDB 1977: 338-350 |
1972 |
5 | | Yahiko Kambayashi,
Shuzo Yajima:
Finite Memory Machines Satisfying the Lower Bound of Memory
Information and Control 20(2): 150-157 (1972) |
4 | | Yahiko Kambayashi,
Shuzo Yajima:
Controllability of Seqential Machines
Information and Control 21(4): 306-328 (1972) |
1971 |
3 | | Yahiko Kambayashi,
Shuzo Yajima:
The Upper Bound of K in K-Lossless Sequential Machines
Information and Control 19(5): 432-438 (1971) |
1970 |
2 | | Toshio Yasui,
Shuzo Yajima:
Two-State Two-Symbol Probabilistic Automata
Information and Control 16(3): 203-224 (1970) |
1969 |
1 | | Toshio Yasui,
Shuzo Yajima:
Some Algebraic Properties of Sets of Stochastic Matrices
Information and Control 14(4): 319-357 (1969) |