14. FPL 2004:
Leuven,
Belgium
Jürgen Becker, Marco Platzner, Serge Vernalde (Eds.):
Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings.
Lecture Notes in Computer Science 3203 Springer 2004, ISBN 3-540-22989-2 BibTeX
@proceedings{DBLP:conf/fpl/2004,
editor = {J{\"u}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {Field Programmable Logic and Application, 14th International
Conference , FPL 2004, Leuven, Belgium, August 30-September 1,
2004, Proceedings},
booktitle = {FPL},
publisher = {Springer},
series = {Lecture Notes in Computer Science},
volume = {3203},
year = {2004},
isbn = {3-540-22989-2},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Plenary Keynotes
Organic and Biology Computing
Security and Cryptography 1
Platform Based Design
Algorithms and Architectures
Acceleration Application 1
Architecture 1
- Alexander Thomas, Jürgen Becker:
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures.
115-124
Electronic Edition (link) BibTeX
- Frederick C. Furtek, Eugene Hogenauer, James Scheuermann:
Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine.
125-134
Electronic Edition (link) BibTeX
- Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini:
Improving FPGA Performance and Area Using an Adaptive Logic Module.
135-144
Electronic Edition (link) BibTeX
- Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan:
A Dual-VDD Low Power FPGA Architecture.
145-157
Electronic Edition (link) BibTeX
Physical Design 1
- Gang Chen, Jason Cong:
Simultaneous Timing Driven Clustering and Placement for FPGAs.
158-167
Electronic Edition (link) BibTeX
- Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng:
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.
168-178
Electronic Edition (link) BibTeX
- Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma:
Compact Buffered Routing Architecture.
179-188
Electronic Edition (link) BibTeX
- Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu:
On Optimal Irregular Switch Box Designs.
189-199
Electronic Edition (link) BibTeX
Arithmetic 1
Multitasking
Circuit Technology
Memory 1
Network Processing
Testing
Applications
Arithmetic 2
Signal Processing 1
Computational Models and Compiler
- Gordon J. Brebner:
Programmable Logic Has More Computational Power than Fixed Logic.
404-413
Electronic Edition (link) BibTeX
- Alexandra Poetter, Jesse Hunter, Cameron Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner:
JHDLBits: The Merging of Two Worlds.
414-423
Electronic Edition (link) BibTeX
- Changchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay Singh:
A System Level Resource Estimation Tool for FPGAs.
424-433
Electronic Edition (link) BibTeX
- Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
The PowerPC Backend Molen Compiler.
434-443
Electronic Edition (link) BibTeX
Dynamic Reconfiguration 1
- Manish Handa, Ranga Vemuri:
An Integrated Online Scheduling and Placement Methodology.
444-453
Electronic Edition (link) BibTeX
- Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker:
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.
454-463
Electronic Edition (link) BibTeX
- Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki:
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
464-473
Electronic Edition (link) BibTeX
- Marcos R. Boschetti, Sergio Bampi, Ivan Saraiva Silva:
Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters.
474-483
Electronic Edition (link) BibTeX
Network and Optimization Algorithms
System-on-Chip 1
High Speed Design
Security and Cryptography 2
Architecture 2
Memory 2
Image Processing 1
Network-on-Chip
Power Aware Design 1
IP-Based Design
Power Aware Design 2
Coprocessing Architectures
- Mihail Petrov, Tudor Murgan, F. May, Martin Vorbach, Peter Zipf, Manfred Glesner:
The XPP Architecture and Its Co-simulation Within the Simulink Environment.
761-770
Electronic Edition (link) BibTeX
- Muhammad Atif Tahir, Ahmed Bouridane, Fatih Kurugollu:
An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer.
771-780
Electronic Edition (link) BibTeX
- Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek:
Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.
781-790
Electronic Edition (link) BibTeX
- Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller:
Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment.
791-800
Electronic Edition (link) BibTeX
Embedded Tutorials
Dynamic Reconfiguration 2
Physical Design 2
Acceleration Application 2
System Level Design
Physical Interconnect
Computational Models
Acceleration Applications 3
Arithmetic 3
Signal Processing 2
System-on-Chip 2
Image Processing 2
Cryptography and Compression
Network Applications and Architectures
- María Dolores Valdés, Miguel A. Domínguez, María José Moure, Camilo Quintáns:
A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses.
1011-1016
Electronic Edition (link) BibTeX
- Philip James-Roxby, Gordon J. Brebner:
Multithreading in a Hyper-programmable Platform for Networked Systems.
1017-1021
Electronic Edition (link) BibTeX
- Ricardo Ferreira, João M. P. Cardoso, Horácio C. Neto:
An Environment for Exploring Data-Driven Architectures.
1022-1026
Electronic Edition (link) BibTeX
- Christian Mannino, Hassan Rabah, Camel Tanougast, Yves Berviller, Michael Janiaut, Serge Weber:
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.
1027-1031
Electronic Edition (link) BibTeX
Network on Chip and Adaptive Architectures
- Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich:
A Dynamic NoC Approach for Communication in Reconfigurable Devices.
1032-1036
Electronic Edition (link) BibTeX
- Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker:
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
1037-1041
Electronic Edition (link) BibTeX
- Leandro Möller, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Eduardo Wenzel Brião, Ewerson Carvalho, Daniel Camozzato:
FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.
1042-1046
Electronic Edition (link) BibTeX
- N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured Methodology for System-on-an-FPGA Design.
1047-1051
Electronic Edition (link) BibTeX
Debugging and Test
- Kris Tiri, Ingrid Verbauwhede:
Secure Logic Synthesis.
1052-1056
Electronic Edition (link) BibTeX
- M. G. Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo:
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.
1057-1061
Electronic Edition (link) BibTeX
- Jonathan Noel Tombs, Miguel Angel Aguirre Echánove, Fernando Muñoz Chavero, Vicente Baena Lecuyer, Antonio Jesús Torralba Silgado, A. Fernandez-León, Francisco Tortosa:
The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead.
1062-1066
Electronic Edition (link) BibTeX
- Andrzej Krasniewski:
Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory.
1067-1072
Electronic Edition (link) BibTeX
Organic and Biology Computing (Poster)
- Chris Clarke, Lin Qiang, Herbert Peremans, Álvaro Hernández:
FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head.
1073-1075
Electronic Edition (link) BibTeX
- Terrence S. T. Mak, K. P. Lam:
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
1076-1079
Electronic Edition (link) BibTeX
- Albert A. Conti, Tom Van Court, Martin C. Herbordt:
Processing Repetitive Sequence Structures with Mismatches at Streaming Rate.
1080-1083
Electronic Edition (link) BibTeX
- Pedro Ferreira, Pedro Ribeiro, Ana Antunes, Fernando Morgado Dias:
Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA.
1084-1086
Electronic Edition (link) BibTeX
- Enrique Cantó, Nicolau Canyellas, Mariano Fons, Francisco Fons, Mariano López:
FPGA Implementation of the Ridge Line Following Fingerprint Algorithm.
1087-1089
Electronic Edition (link) BibTeX
Security and Cryptography (Poster)
- Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner:
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals.
1090-1092
Electronic Edition (link) BibTeX
- David Nguyen, Joseph Zambreno, Gokhan Memik:
Flow Monitoring in High-Speed Networks with 2D Hash Tables.
1093-1097
Electronic Edition (link) BibTeX
- Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
A VHDL Generator for Elliptic Curve Cryptography.
1098-1100
Electronic Edition (link) BibTeX
- Alessandro Bogliolo, Valerio Freschi, Filippo Miglioli, Matteo Canella:
FPGA-Based Parallel Comparison of Run-Length-Encoded Strings.
1101-1103
Electronic Edition (link) BibTeX
- Juan Manuel García Chamizo, Andrés Fuster Guilló, Jorge Azorín López:
Real Environments Image Labelling Based on Reconfigurable Architectures.
1104-1106
Electronic Edition (link) BibTeX
Mapping and Compilers (Poster)
- Jan Borgosz:
Object Oriented Programming Paradigms for the VHDL.
1107-1109
Electronic Edition (link) BibTeX
- Ivan Gonzalez, Javier Sanchez-Pastor, Jorge L. Hernandez-Ardieta, Francisco J. Gomez-Arribas, Javier Martínez:
Using Reconfigurable Hardware Through Web Services in Distributed Applications.
1110-1112
Electronic Edition (link) BibTeX
- Nastaran Baradaran, Joonseok Park, Pedro C. Diniz:
Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract.
1113-1115
Electronic Edition (link) BibTeX
- K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis:
A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development.
1116-1118
Electronic Edition (link) BibTeX
- Pierre Niang, Thierry Grandpierre, Mohamed Akil, Yves Sorel:
AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits.
1119-1123
Electronic Edition (link) BibTeX
Architectures (Poster)
- Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga:
A Self-Reconfiguration Framework for Multiprocessor CSoPCs.
1124-1126
Electronic Edition (link) BibTeX
- Adam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger:
A Virtual File System for Dynamically Reconfigurable FPGAs.
1127-1129
Electronic Edition (link) BibTeX
- Tapio Ristimäki, Jari Nurmi:
Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array.
1130-1132
Electronic Edition (link) BibTeX
- Tomás Marek, Martin Novotný, Ludek Crha:
Design and Implementation of the Memory Scheduler for the PC-Based Router.
1133-1135
Electronic Edition (link) BibTeX
Algorithms and IP (Poster)
mage Processing (Poster)
- Viorela Ila, Rafael García, François Charot, Joan Batlle:
FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot.
1152-1154
Electronic Edition (link) BibTeX
- Hiroaki Niitsuma, Tsutomu Maruyama:
Real-Time Detection of Moving Objects.
1155-1157
Electronic Edition (link) BibTeX
- Sonia Mota, Eduardo Ros, Javier Díaz, Eva M. Ortigosa, Rodrigo Agís, Richard R. Carrillo:
Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs.
1158-1161
Electronic Edition (link) BibTeX
- Pierre Chalimbaud, François Berry:
Versatile Imaging Architecture Based on a System on Chip.
1162-1164
Electronic Edition (link) BibTeX
- Constantinos Skarpathiotis, Keith R. Dimond:
A Hardware Implementation of a Content Based Image Retrieval Algorithm.
1165-1167
Electronic Edition (link) BibTeX
PhD Forum (Poster)
Copyright © Sat May 16 23:12:42 2009
by Michael Ley (ley@uni-trier.de)
