N. Pete Sedcole

2008
18	EE	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258
17	EE	N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Measuring and modeling FPGA clock variability. FPGA 2008: 258
16	EE	Edward Stott, N. Pete Sedcole, Peter Y. K. Cheung: Fault tolerant methods for reliability in FPGAs. FPL 2008: 415-420
15	EE	Justin S. Wong, Peter Y. K. Cheung, N. Pete Sedcole: Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704
14	EE	N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheung: Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328
13	EE	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214
12	EE	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10
11	EE	Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58
10	EE	N. Pete Sedcole, Peter Y. K. Cheung: Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. TRETS 1(2): (2008)
2007
9	EE	N. Pete Sedcole, Peter Y. K. Cheung: Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA 2007: 178-187
8	EE	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, K. P. Lam: A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182
7	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. VLSI Syst. 15(9): 1003-1016 (2007)
2006
6	EE	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8
5	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176
2005
4		N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght: Modular Partial Reconfiguration in Virtex FPGAs. FPL 2005: 211-216
2004
3	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272
2	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051
2003
1	EE	N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk: A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615

Coauthor Index

1	James Anderson	[4]
2	Tobias Becker	[4]
3	Brandon Blodget	[4]
4	Peter Y. K. Cheung	[1] [2] [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]
5	George A. Constantinides	[1] [2] [3] [5] [7]
6	Crescenzo D'Alessandro	[11] [13]
7	K. P. Lam	[8]
8	Wayne Luk	[1] [2] [3] [5] [6] [7] [8] [11] [12] [13] [18]
9	Patrick Lysaght	[4]
10	Terrence S. T. Mak	[6] [8] [11] [12] [13] [18]
11	Edward Stott	[16]
12	Justin S. Wong	[14] [15] [17]
13	Alexandre Yakovlev	[11] [13]