| 2007 |
|---|
| 12 | EE | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems
CoRR abs/0710.4850: (2007) |
| 2005 |
|---|
| 11 | EE | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Enhanced Function Allocation Management in Reconfigurable Systems.
IPDPS 2005 |
| 10 | EE | Michael Ullmann,
Michael Hübner,
Jürgen Becker:
On-demand FPGA run-time system for flexible and dynamical reconfiguration.
IJES 1(3/4): 193-204 (2005) |
| 9 | EE | Michael Hübner,
Michael Ullmann,
Jürgen Becker:
Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation.
IJES 1(3/4): 263-273 (2005) |
| 8 | EE | Jürgen Becker,
Kurt Brändle,
Michael Ullmann:
Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen.
it - Information Technology 47(4): 201-206 (2005) |
| 2004 |
|---|
| 7 | EE | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems.
DATE 2004: 259-264 |
| 6 | EE | Michael Ullmann,
Wansheng Jin,
Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems.
DATE 2004: 259-264 |
| 5 | EE | Michael Hübner,
Michael Ullmann,
Lars Braun,
A. Klausmann,
Jürgen Becker:
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.
FPL 2004: 1037-1041 |
| 4 | EE | Michael Ullmann,
Michael Hübner,
Björn Grimm,
Jürgen Becker:
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities.
FPL 2004: 454-463 |
| 3 | EE | Michael Ullmann,
Michael Hübner,
Björn Grimm,
Jürgen Becker:
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration.
IPDPS 2004 |
| 2003 |
|---|
| 2 | EE | Jürgen Becker,
Michael Hübner,
Michael Ullmann:
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations.
SBCCI 2003: 283-288 |
| 1 | | Jürgen Becker,
Michael Hübner,
Michael Ullmann:
Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations.
VLSI-SOC 2003: 129- |
