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Milan Vasilko

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2006
15EENicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100
14EEPiotr Stepien, Milan Vasilko: On Feasibility of FPGA Bitstream Compression During Placement and Routing. FPL 2006: 1-4
13EENicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6
2005
12EENicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148
11 Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko: Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414
2004
10EENicola Campregher, Peter Y. K. Cheung, Milan Vasilko: BIST Based Interconnect Fault Location for FPGAs. FPL 2004: 322-332
2002
9EETero Rissa, Milan Vasilko, Jarkko Niittylahti: System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems. FCCM 2002: 295-296
2001
8EEMilan Vasilko, L. Machácek, M. Matej, Piotr Stepien, S. Holloway: A Rapid Prototyping Methodology and Platform for Seamless Communication Systems. IEEE International Workshop on Rapid System Prototyping 2001: 70-76
2000
7EEMilan Vasilko: Design Visualisation for Dynamically Reconfigurable Systems. FPL 2000: 131-140
6EEMilan Vasilko, Graham Benyon-Tinker: Automatic Temporal Floorplanning with Guaranteed Solution Feasibility. FPL 2000: 656-664
1999
5EEMilan Vasilko, David Cabanis: Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic Systems. FCCM 1999: 123-
4 Milan Vasilko: DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems. FPL 1999: 124-133
1998
3EEMilan Vasilko, D. Long: RIFLE-62: A Flexible Environment for Prototyping Dynamically Reconfigurable Systems. International Workshop on Rapid System Prototyping 1998: 130-135
1996
2 Milan Vasilko, Djamel Ait-Boudaoud: Optically Reconfigurable FPGAs: Is this a Future Trend? FPL 1996: 270-279
1 Milan Vasilko, Djamel Ait-Boudaoud: Architectural Synthesis Techniques for Dynamically Reconfigurable Logic. FPL 1996: 290-296

Coauthor Index

1Djamel Ait-Boudaoud [1] [2]
2Graham Benyon-Tinker [6]
3David Cabanis [5]
4Nicola Campregher [10] [11] [12] [13] [15]
5Peter Y. K. Cheung [10] [11] [12] [13] [15]
6George A. Constantinides [11] [12] [13] [15]
7S. Holloway [8]
8D. Long [3]
9L. Machácek [8]
10M. Matej [8]
11Jarkko Niittylahti [9]
12Tero Rissa [9]
13Piotr Stepien [8] [14]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)