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Jürgen Becker

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2009
142EEJürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings Springer 2009
141EEKrzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker: FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC 2009: 62-73
2008
140EEOliver Sander, Lars Braun, Michael Hübner, Jürgen Becker: Data reallocation by exploiting FPGA configuration mechanisms. ARC 2008: 308-313
139EEAlexander Klimm, Oliver Sander, Jürgen Becker, Sylvain Subileau: A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA. ARCS 2008: 188-201
138EEAntonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, P. Millet, Matthias Kühnle, F. Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, T. DeMarco: Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. DATE 2008: 1352-1357
137EEKatarina Paulsson, Michael Hübner, Jürgen Becker: Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. DATE 2008: 50-55
136EEBenjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker: A System Architecture for Reconfigurable Trusted Platforms. DATE 2008: 541-544
135EERalf König, Timo Stripf, Jürgen Becker: A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. DATE 2008: 604-609
134EEJürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer: Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE 2008
133EECarlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker: Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. FCCM 2008: 320-321
132EEJosef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348
131EESven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
130EEDiana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker: New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. FPL 2008: 495-498
129EEChristopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker: A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538
128EELars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker: Data path driven waveform-like reconfiguration. FPL 2008: 607-610
127EEKatarina Paulsson, Michael Hübner, Jürgen Becker: Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. FPL 2008: 699-700
126EEBenjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker: A self adaptive interfacing concept for consumer device integration into automotive entities. IPDPS 2008: 1-6
125EEMichael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker: Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. IPDPS 2008: 1-6
124EEChristian Schuck, Matthias Kühnle, Michael Hübner, Jürgen Becker: A framework for dynamic 2D placement on FPGAs. IPDPS 2008: 1-7
123EEAlexander Klimm, Lars Braun, Jürgen Becker: An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. IPDPS 2008: 1-7
122EEDiana Göhringer, Michael Hübner, Volker Schatz, Jürgen Becker: Runtime adaptive multi-processor system-on-chip: RAMPSoC. IPDPS 2008: 1-7
121EEJürgen Becker: Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. ISVLSI 2008: 1-2
120EEKatarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker: Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. ISVLSI 2008: 304-309
119EESunil Shukla, Neil W. Bergmann, Jürgen Becker: A Web Server Based Edge Detector Implementation in FPGA. ISVLSI 2008: 441-446
118EEJuanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker: Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS 2008: 419-428
117EECarlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker: Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. SASP 2008: 34-41
2007
116EEKatarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker: Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. FPL 2007: 351-356
115EEChristian Schuck, Stefan Lamparth, Jürgen Becker: artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. FPL 2007: 371-376
114EEFlorian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker: MORPHEUS: Heterogeneous Reconfigurable Computing. FPL 2007: 409-414
113EEKatarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat: On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. FPL 2007: 415-422
112EEMahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker: H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. FPL 2007: 467-471
111EELars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach: Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. FPL 2007: 688-691
110EEPhilipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker: A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. FPL 2007: 722-725
109EEAlisson V. De Brito, Matthias Kühnle, Elmar U. K. Melcher, Jürgen Becker: A General Purpose Partially Reconfigurable Processor Simulator (PReProS). IPDPS 2007: 1-7
108EESunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. IPDPS 2007: 1-7
107EEThilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker: Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS 2007: 1-8
106EEMaik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker: High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS 2007: 1-8
105EECarlos Morra, João M. P. Cardoso, Jürgen Becker: Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. IPDPS 2007: 1-8
104EEAlisson V. De Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher: Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. ISVLSI 2007: 35-40
103EEMichael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele: Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46
102 Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker: Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoC 2007: 1-6
101EEJürgen Becker, Adam Donlin, Michael Hübner: New tool support and architectures in adaptive reconfigurable computing. VLSI-SoC 2007: 134-139
100EEMichael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems CoRR abs/0710.4850: (2007)
99EEAlexander Thomas, Jürgen Becker: New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). it - Information Technology 49(3): 165- (2007)
2006
98 Claudionor José Nunes Coelho Jr., Ricardo P. Jacobi, Jürgen Becker: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006 ACM 2006
97 Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle: ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany GI 2006
96 Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich: Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006 Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006
95EEKatarina Paulsson, Michael Hübner, Jürgen Becker: Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. AHS 2006: 288-291
94EESunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. ARC 2006: 93-98
93 Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn: Digital On-Demand Computing Organism for Real-Time Systems. ARCS Workshops 2006: 230-245
92EEJürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
91EEJürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas: 06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
90EEJürgen Becker, Michael Hübner, Katarina Paulsson: Physical 2D Morphware and Power Reduction Methods for Everyone. Dynamically Reconfigurable Architectures 2006
89EESunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Coarse Grained Paradigm for FPGAs. Dynamically Reconfigurable Architectures 2006
88EECarlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein: From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4
87EEMaik Boden, Steffen Rülke, Jürgen Becker: A high-level target-precise model for designing reconfigurable HW tasks. IPDPS 2006
86EEMichael Hübner, Christian Schuck, Jürgen Becker: Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. IPDPS 2006
85EESunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Two-Level Reconfigurable Architecture. ISVLSI 2006: 109-116
84EEKatarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker: Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. ISVLSI 2006: 159-166
83EEPascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker: Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. ISVLSI 2006: 251-256
82EEMichael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker: New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. ISVLSI 2006: 97-102
81 Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein: Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC 2006: 46-51
80EEMichael Hübner, Jürgen Becker: Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. SBCCI 2006: 1-4
79EEKatarina Paulsson, Michael Hübner, Jürgen Becker: On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. SBCCI 2006: 173-178
78EEJürgen Becker, Michael Hübner: Run-time reconfigurabilility and other future trends. SBCCI 2006: 9-11
2005
77 Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic: Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
76 Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Christian Hochberger, Thomas Martinetz, Christian Müller-Schloer, Hartmut Schmeck, Theo Ungerer, Rolf P. Würtz: 18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005 VDE Verlag 2005
75 Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker: Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. ARCS Workshops 2005: 39-44
74 Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein: FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL 2005: 25-30
73 Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon: Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. FPL 2005: 703-706
72EEMichael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Enhanced Function Allocation Management in Reconfigurable Systems. IPDPS 2005
71EEMichael Hübner, Katarina Paulsson, Jürgen Becker: Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. IPDPS 2005
70EEAlexander Thomas, Jürgen Becker: Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. ISVLSI 2005: 118-123
69EECarsten Bieser, Klaus D. Müller-Glaser, Jürgen Becker: Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling. MSE 2005: 51-52
68 Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas: Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. ReCoSoC 2005: 35-42
67EEJürgen Becker, Alexander Thomas: Scalable Processor Instruction Set Extension. IEEE Design & Test of Computers 22(2): 136-148 (2005)
66EEMichael Ullmann, Michael Hübner, Jürgen Becker: On-demand FPGA run-time system for flexible and dynamical reconfiguration. IJES 1(3/4): 193-204 (2005)
65EEMichael Hübner, Michael Ullmann, Jürgen Becker: Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation. IJES 1(3/4): 263-273 (2005)
64EEJürgen Becker, Kurt Brändle, Michael Ullmann: Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen. it - Information Technology 47(4): 201-206 (2005)
2004
63 Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, Thomas A. Runkler: ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany GI 2004
62 Jürgen Becker, Marco Platzner, Serge Vernalde: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings Springer 2004
61 Alexander Thomas, Jürgen Becker: Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. ARCS Workshops 2004: 165-174
60EEMichael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. DATE 2004: 259-264
59EEMichael Ullmann, Wansheng Jin, Jürgen Becker: Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. DATE 2004: 259-264
58EEMichael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker: Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. FPL 2004: 1037-1041
57EEAlexander Thomas, Jürgen Becker: Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. FPL 2004: 115-124
56EEMichael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. FPL 2004: 454-463
55 Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer: CARUSO - Project Goals and Principal Approach. GI Jahrestagung (2) 2004: 616-620
54EEMichael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker: An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. IPDPS 2004
53EEUwe Brinkschulte, Jürgen Becker, Theo Ungerer: CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application. IPDPS 2004
52EEAlexander Thomas, Thomas Zander, Jürgen Becker: Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. SBCCI 2004: 141-146
51EEMichael Hübner, Tobias Becker, Jürgen Becker: Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. SBCCI 2004: 28-32
50EEJürgen Becker: Dagstuhl-Seminar "Dynamically and Partially Reconfigurable Architectures". it - Information Technology 46(4): 218-225 (2004)
2003
49EEJürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten: An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. DATE 2003: 11120-11121
48 Jürgen Becker, Martin Vorbach: PACT XPP Architecture in Adaptive System-on-Chip Integration. Engineering of Reconfigurable Systems and Algorithms 2003: 21-30
47EEMartin Vorbach, Jürgen Becker: Reconfigurable Processor Architectures for Mobile Phones. IPDPS 2003: 181
46EEJürgen Becker, Martin Vorbach: Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). ISVLSI 2003: 107-112
45EEJens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker: Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. MSE 2003: 134-135
44EEJürgen Becker, Alexander Thomas, Maik Scheer: Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. SBCCI 2003: 237-242
43EEJürgen Becker, Michael Hübner, Michael Ullmann: Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. SBCCI 2003: 283-288
42 Jürgen Becker, Michael Hübner, Michael Ullmann: Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. VLSI-SOC 2003: 129-
41 Jürgen Becker, Alexander Thomas, Maik Scheer: Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. VLSI-SOC 2003: 288-
40EEJürgen Becker, Reiner W. Hartenstein: Configware and morphware going mainstream. Journal of Systems Architecture 49(4-6): 127-142 (2003)
2002
39EEChun Hok Ho, M. P. Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner: Rapid Prototyping of FPGA Based Floating Point DSP Systems. IEEE International Workshop on Rapid System Prototyping 2002: 19-24
2001
38EEJürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner: Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL 2001: 584-589
37EEAmar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner: Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. IEEE International Workshop on Rapid System Prototyping 2001: 58-63
36EEJochen Mades, T. Schneider, A. Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner: Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE 2001: 2-3
35 Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis: Distributed Collaborative Design over Cave2 Framework. VLSI-SOC 2001: 97-108
34 Jürgen Becker, Manfred Glesner: A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. The Journal of Supercomputing 19(1): 105-127 (2001)
2000
33EEAhmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner: Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. FCCM 2000: 205-216
32EEJürgen Becker, Thilo Pionteck, Manfred Glesner: DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL 2000: 312-321
31EEFrank-Michael Renner, Jürgen Becker, Manfred Glesner: Field Programmable Communication Emulation and Optimization for Embedded System Design. FPL 2000: 58-67
30EEFrank-Michael Renner, Jürgen Becker, Manfred Glesner: Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 2000: 154-159
29EEJürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner: Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. IEEE International Workshop on Rapid System Prototyping 2000: 160-
28 Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk: Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. PDPTA 2000
27 Jürgen Becker, Manfred Glesner: IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. PDPTA 2000
1999
26 Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu: Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. ARCS 1999: 143-154
25 Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker: Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. FPL 1999: 507-513
24EEFrank-Michael Renner, Jürgen Becker, Manfred Glesner: Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 1999: 108-113
23 Andreas Kirschbaum, Jürgen Becker, Manfred Glesner: ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. VLSI 1999: 659-670
1998
22 Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger: Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC 1998: 23-33
21EEThomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner: HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES 1998: 29-33
20EEFrank-Michael Renner, Jürgen Becker, Manfred Glesner: An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. FPL 1998: 179-188
19EEJürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner: Perspectives of Reconfigurable Computing in Research, Industry and Education. FPL 1998: 39-48
18 Andreas Kirschbaum, Jürgen Becker, Manfred Glesner: A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. IPPS/SPDP Workshops 1998: 61-66
17EEJürgen Becker, Reiner W. Hartenstein: Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping 1998: 32-38
16EEAndreas Kirschbaum, Jürgen Becker, Manfred Glesner: Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. International Workshop on Rapid System Prototyping 1998: 52-57
1997
15 Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: A Novel Universal Sequencer Hardware. ARCS 1997: 143-152
14EEReiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: A Novel Sequencer Hardware for Application Specific Computing. ASAP 1997: 392-401
13EEReiner W. Hartenstein, Jürgen Becker: Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES 1997: 141-146
12 Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger: Data scheduling to increase performance of parallel accelerators. FPL 1997: 294-303
11EEReiner W. Hartenstein, Jürgen Becker: A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) 1997: 125-134
10EEReiner W. Hartenstein, Jürgen Becker: Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design 1997: 146-150
1996
9EEReiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger: A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283
8EEReiner W. Hartenstein, Jürgen Becker, Rainer Kress: Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES 1996: 77-84
7EEReiner W. Hartenstein, Jürgen Becker, Rainer Kress: Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS 1996: 395-
6 Reiner W. Hartenstein, Jürgen Becker, Rainer Kress: Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL 1996: 65-76
5EEReiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger: A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548
4EEReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84
3 Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig: High-performance computing using a reconfigurable accelerator. Concurrency - Practice and Experience 8(6): 429-443 (1996)
1995
2EEReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt: A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132
1994
1 Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt: Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195

Coauthor Index

1Carsten Albrecht [107]
2Ahmad Alsolaim [28] [33]
3Josef Angermeier [132]
4Hamid R. Arabnia [77]
5Andreas Ast [1]
6Peter M. Athanas (Peter Athanas) [91] [92] [96] [142]
7Günther Auer [116]
8Mauricio Ayala-Rincón [74]
9Stefan Bach [111]
10Volker Baumgarten [49]
11Salih Bayar [102]
12Jens E. Becker [45]
13Tobias Becker [51]
14Pascal Benoit [73] [83]
15Neil W. Bergmann [85] [89] [94] [108] [119]
16Koen Bertels [114]
17Carsten Bieser [45] [69]
18João Bispo [117] [133]
19Maik Boden [87] [106]
20Philippe Bonnot [114] [138]
21Kurt Brändle [64] [93]
22Lars Braun [58] [103] [111] [123] [125] [128] [129] [132] [140] [141]
23Gordon J. Brebner [91] [92] [96]
24Uwe Brinkschulte [53] [55] [63] [76] [93]
25Alisson V. De Brito [104] [109]
26Gaston Cambon [73] [83]
27Fabio Campi [138]
28Tri Caohuu [25] [26]
29João M. P. Cardoso [105] [117] [133]
30Christopher Claus [103] [129] [132]
31Claudionor José Nunes Coelho Jr. [98]
32Massimo Coppola [138]
33T. DeMarco [138]
34Antonio Deledda [138]
35Adam Donlin [101]
36Klaus Dorfmüller-Ulhaas [55]
37Michael Dreschmann [116]
38Hritam Dutta [131]
39Sven Eisenhardt [131]
40Robert Esser [118] [134]
41Dietmar Fey [63] [76]
42Thomas Fiebig [106]
43Julio A. de Oliveira Filho [131]
44A. Friebe [37]
45Christian Gamrat [113]
46Mahendra Kumar Angamuthu Ganesan [112]
47Benjamin Glas [126] [136]
48Manfred Glesner [16] [18] [19] [20] [21] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [131]
49Diana Göhringer [122] [125] [130]
50Sebastian Goller [114]
51Philipp Graf [110] [132]
52Arnaud Grasset [138]
53Björn Grimm [54] [56]
54Karl-Erwin Großpietsch [63] [97]
55Stéphane Guyetant [114]
56C. Habermann [37]
57Frank Hannig [131]
58Reiner W. Hartenstein [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [22] [40] [74] [81] [88]
59Jörg Henkel [93]
60Andreas Herkersdorf [132] [134]
61Michael Herz [5] [9] [12] [14] [15] [22]
62Heiko Hinkelmann [131]
63Chun Hok Ho [39]
64Christian Hochberger [63] [76] [97]
65Thomas Hollstein [21] [36]
66Michael Hübner [42] [43] [51] [54] [56] [58] [65] [66] [68] [71] [75] [78] [79] [80] [82] [84] [86] [90] [95] [101] [102] [103] [104] [107] [110] [111] [113] [116] [118] [120] [122] [124] [125] [127] [128] [129] [130] [132] [134] [137] [138] [140] [141]
67Masaharu Imai [77]
68Leandro Soares Indrusiak [35]
69Ricardo P. Jacobi [98]
70Wansheng Jin [59] [60] [72] [100]
71Markus Jung [84]
72Lukusa D. Kabulepa [29]
73Wolfgang Karl [93] [97]
74Krzysztof Kepa [141]
75Andreas Kirschbaum [16] [18] [19] [21] [23]
76Dmitrij Kissler [131]
77A. Klausmann [58]
78Alexander Klimm [123] [126] [136] [139]
79Roman Koch [107]
80Ralf König [55] [135]
81Krzysztof Kosciuszkiewicz [141]
82Thorsten Köster [93]
83Rainer Kress [1] [2] [3] [4] [5] [6] [7] [8] [9]
84Herrmann Krömer [128]
85Matthias Kühnle [82] [104] [109] [114] [124] [138]
86Stefan Lamparth [115]
87Vera Lauer [134]
88Thuy Trong Le [25]
89M. P. Leong [39]
90Philip Heng Wai Leong [39]
91Nicolas Liebau [38]
92Riccardo Locatelli [138]
93Enno Lübbers [132]
94Jochen Mades [36]
95Erik Maehle [63] [97] [107]
96Mateusz Majer [132]
97Thomas Martinetz [76]
98Giuseppe Maruccia [138]
99Frank May [112]
100Torsten Meibner [106]
101Elmar U. K. Melcher [104] [109]
102Renate Merker [132]
103P. Millet [138]
104Fearghal Morgan [141] [142]
105Carlos Morra [74] [81] [88] [105] [117] [133]
106Nitin Motgi [37]
107Claudio Mucci [138]
108Amar Mukherjee [37]
109Klaus D. Müller-Glaser [45] [69] [110] [114] [126] [136]
110Christian Müller-Schloer [76]
111Ulrich Nageldinger [5] [9] [12] [14] [15] [22]
112Juanjo Noguera [118]
113Tobias Oppold [131]
114Elena Moscu Panainte [114]
115Katarina Paulsson [68] [71] [75] [79] [84] [90] [95] [102] [113] [116] [118] [120] [127] [128] [137]
116Thomas Perschke [111] [130]
117Jean-Marc Philippe [113]
118Lorenzo Pieralisi [138]
119Thilo Pionteck [32] [38] [107]
120Marco Platzner [62] [132]
121Helmut Reinig [1] [2] [3] [4]
122Ricardo Augusto da Luz Reis (Ricardo A. L. Reis, Ricardo Reis) [35]
123Frank-Michael Renner [19] [20] [24] [29] [30] [31]
124F. Ries [138]
125Michel Robert [73] [83]
126Wolfgang Rosenstiel [131]
127Steffen Rülke [87] [106]
128Markus Rullmann [132]
129Thomas A. Runkler [63]
130M. Sackmann [81] [88]
131Zoran A. Salcic [77]
132Oliver Sander [126] [136] [139] [140]
133Gilles Sassatelli [73] [83]
134Volker Schatz [111] [122]
135Maik Scheer [41] [44]
136Hartmut Schmeck [76]
137Karin Schmidt [1] [2]
138Axel Schneider [114]
139T. Schneider [36]
140Christian Schuck [82] [86] [115] [124]
141Eberhard Schüler [114]
142T. Schwalb [132]
143Thomas Schweizer [131]
144Sunil Shukla [85] [88] [89] [94] [108] [119]
145Sundeep Singh [112]
146Janusz A. Starzyk [28] [33]
147Walter Stechele [103] [129] [132] [134]
148Marcus Stitz [75]
149Timo Stripf [135]
150Sylvain Subileau [139]
151Jürgen Teich [91] [92] [96] [131] [132]
152Marc Theisen [26]
153Florian Thoma [114]
154Alexander Thomas [41] [44] [45] [49] [52] [57] [61] [67] [68] [70] [99] [131]
155Lionel Torres [73] [83]
156Sascha Uhrig [55]
157Michael Ullmann [42] [43] [54] [56] [58] [59] [60] [64] [65] [66] [72] [100]
158Theo Ungerer [53] [55] [76]
159Serge Vernalde [62]
160Ulrich Viereck [120]
161Arseni Vitkovski [138]
162Martin Vorbach [46] [47] [48] [49]
163Michael Wenz [93]
164A. Windisch [36]
165Roger Woods (Roger F. Woods) [142]
166Heinz Wörn [93]
167Rolf P. Würtz [76]
168Laurence Tianruo Yang [77]
169Thomas Zander [52]
170Bin Zhang [129]
171Peter Zipf [131]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)