| 2008 |
|---|
| 9 | EE | Miguel L. Silva,
João Canas Ferreira:
Generation of partial FPGA configurations at run-time.
FPL 2008: 367-372 |
| 2006 |
|---|
| 8 | EE | Miguel L. Silva,
João Canas Ferreira:
Support for partial run-time reconfiguration of platform FPGAs.
Journal of Systems Architecture 52(12): 709-726 (2006) |
| 2005 |
|---|
| 7 | EE | Miguel L. Silva,
João Canas Ferreira:
Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs.
DSD 2005: 383-387 |
| 6 | EE | João Canas Ferreira,
Miguel M. Silva:
Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer.
IPDPS 2005 |
| 2004 |
|---|
| 5 | EE | João Canas Ferreira,
José Silva Matos:
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware.
FPL 2004: 886-890 |
| 1999 |
|---|
| 4 | EE | José Carlos Alves,
João Canas Ferreira,
C. Albuquerque,
José F. Oliveira,
J. Soeiro Ferreira,
José Silva Matos:
FAFNER-Accelerating Nesting Problems with FPGAs.
FCCM 1999: 168- |
| 1998 |
|---|
| 3 | EE | João Canas Ferreira,
José Silva Matos:
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware.
FCCM 1998: 280-281 |
| 1994 |
|---|
| 2 | | José Silva Matos,
João Canas Ferreira,
Ana C. Leão,
José Machado da Silva:
An Approach to Testability Improvement of Mixed-Signal Boards.
ISCAS 1994: 161-164 |
| 1993 |
|---|
| 1 | | José Silva Matos,
Ana C. Leão,
João Canas Ferreira:
Control and Observation of Analog Nodes in Mixed-Signal Boards.
ITC 1993: 323-331 |
