2009 |
19 | EE | Mario García-Valderas,
Luis Entrena,
Raúl Fernández Cardenal,
Celia López-Ongil,
Marta Portela-García:
SET Emulation Under a Quantized Delay Model.
J. Electronic Testing 25(1): 107-116 (2009) |
2007 |
18 | EE | Mario García-Valderas,
Raúl Fernández Cardenal,
Celia López-Ongil,
Marta Portela-García,
Luis Entrena:
SET Emulation Under a Quantized Delay Model.
DFT 2007: 68-77 |
17 | EE | Marta Portela-García,
Celia López-Ongil,
Mario García-Valderas,
Luis Entrena:
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors.
IOLTS 2007: 101-106 |
16 | EE | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
CoRR abs/0710.4757: (2007) |
2006 |
15 | | Mario García-Valderas,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena-Arrontes:
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories.
DDECS 2006: 218-219 |
14 | EE | Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena:
Fault Injection-based Reliability Evaluation of SoPCs.
European Test Symposium 2006: 75-82 |
13 | EE | Mario García-Valderas,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena:
Emulation-based Fault Injection in Circuits with Embedded Memories.
IOLTS 2006: 183-184 |
2005 |
12 | EE | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation.
DATE 2005: 308-309 |
11 | | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation.
FPL 2005: 397-402 |
10 | | Almudena Lindoso,
Luis Entrena,
Celia López-Ongil,
Judith Liu-Jimenez:
Correlation-Based Fingerprint Matching Using FPGAs.
FPT 2005: 87-94 |
9 | EE | Celia López-Ongil,
Mario García-Valderas,
Marta Portela-García,
Luis Entrena-Arrontes:
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading.
IOLTS 2005: 43-48 |
2004 |
8 | EE | Celia López-Ongil,
Raul Sánchez-Reillo,
Judith Liu-Jimenez,
Fernando Casado,
Leslie Sánchez,
Luis Entrena:
FPGA Implementation of Biometric Authentication System Based on Hand Geometry.
FPL 2004: 43-53 |
7 | EE | Mario García-Valderas,
Celia López-Ongil,
Marta Portela-García,
Luis Entrena:
Transient Fault Emulation of Hardened Circuits in FPGA Platforms.
IOLTS 2004: 109-114 |
2003 |
6 | EE | Enrique San Millán,
Luis Entrena,
José Alberto Espejo,
Celia López:
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques.
Journal of Systems Architecture 49(12-15): 529-541 (2003) |
2002 |
5 | EE | Luis Berrojo,
Isabel González,
Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Luis Entrena,
Celia López:
New Techniques for Speeding-Up Fault-Injection Campaigns.
DATE 2002: 847-853 |
4 | EE | Luis Berrojo,
Isabel González,
Luis Entrena,
Celia López,
Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level.
IOLTW 2002: 193 |
3 | EE | Luis Berrojo,
Isabel González,
Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Luis Entrena,
Celia López:
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation.
VTS 2002: 229-236 |
2001 |
2 | EE | Luis Entrena,
Celia López,
Emilio Olías,
Enrique San Millán,
José Alberto Espejo:
Logic Optimization of Unidirectional Circuits with Structural Methods.
IOLTW 2001: 43-47 |
1 | EE | Luis Entrena,
Celia López,
Emilio Olías:
Automatic Insertion of Fault-Tolerant Structures at the RT Level.
IOLTW 2001: 48-50 |