David M. Lewis

2005
29	EE	David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20
2004
28	EE	Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144
2003
27	EE	David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose: The StratixTM routing and logic architecture. FPGA 2003: 12-20
2002
26	EE	Guy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28
25	EE	Guy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131
2001
24	EE	Guy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68
2000
23	EE	L. Louis Zhang, Qiang Wang, David M. Lewis: Design of a VLIW Compute Accelerator on the Transmogrifier-2. FCCM 2000: 3-12
22	EE	Guy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
1999
21	EE	Andy Gean Ye, David M. Lewis: Procedural Texture Mapping on FPGAs. FPGA 1999: 112-120
1998
20	EE	David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. VLSI Syst. 6(2): 188-198 (1998)
1997
19	EE	Qiang Wang, David M. Lewis: Automated field-programmable compute accelerator design using partial evaluation. FCCM 1997: 145-154
18	EE	David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow: The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61
1996
17	EE	Vi Cuong Chan, David M. Lewis: Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays. FPGA 1996: 51-57
1994
16		Aditya A. Aggarwal, David M. Lewis: Routing Architectures for Hierarchical Field Programmable Gate Arrays. ICCD 1994: 475-478
15		David M. Lewis: Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit. IEEE Trans. Computers 43(8): 974-982 (1994)
1993
14		David M. Lewis, Marcus van Ierssel, Daniel H. Wong: A Field Programmable Accelerator for Compiled-Code Applications. ICCD 1993: 491-496
13	EE	David M. Lewis: An accurate LNS arithmetic unit using interleaved memory function interpolator. IEEE Symposium on Computer Arithmetic 1993: 2-9
12		David A. Johns, David M. Lewis, D. Cherepacha: Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering. ISCAS 1993: 1302-1305
11	EE	Ahmet N. Parlakbilek, David M. Lewis: A multiple-strength multiple-delay compiled-code logic simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1937-1946 (1993)
1992
10	EE	David M. Lewis: A compiled-code hardware accelerator for circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 555-565 (1992)
1991
9		Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White: Hector: A Hierarchically Structured Shared-memory Multiprocessor. IEEE Computer 24(1): 72-79 (1991)
8	EE	David M. Lewis: A hierarchical compiled code event-driven logic simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 726-737 (1991)
1990
7		Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis: Using Deducibility in Secure Network Modelling. ESORICS 1990: 117-123
6		David M. Lewis: An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. IEEE Trans. Computers 39(11): 1325-1336 (1990)
5	EE	David M. Lewis: Device model approximation using 2N trees. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 30-38 (1990)
1988
4	EE	David M. Lewis: A Programmable Hardware Accelerator for Compiled Electrical Simulation. DAC 1988: 172-177
3	EE	David M. Lewis: Hardware accelerators for timing simulation of VLSI digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 7(11): 1134-1149 (1988)
1986
2		David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson: Swamp: A Fast Processor for Smalltalk-80. OOPSLA 1986: 131-139
1985
1	EE	David M. Lewis: A hardware engine for analogue mode simulation of MOS digital circuits. DAC 1985: 345-351

Coauthor Index

1	Aditya A. Aggarwal	[16]
2	Elias Ahmed	[29]
3	Gregg Baeckler	[28] [29]
4	Vaughn Betz	[27] [29]
5	Peter I. P. Boulton	[7]
6	Mark Bourgeault	[28] [29]
7	David Cashman	[29]
8	Vi Cuong Chan	[17]
9	D. Cherepacha	[12]
10	Paul Chow	[18] [20]
11	Richard Cliff	[27] [29]
12	Robert J. Francis	[2]
13	David R. Galloway	[2] [18] [20] [29]
14	Michael Hutton (Michael D. Hutton, Mike Hutton)	[28] [29]
15	Marcus van Ierssel	[14] [18] [20]
16	David Jefferson	[27]
17	David A. Johns	[12]
18	Sinan Kaptanoglu	[28]
19	Henry Kim	[28]
20	Christopher Lane	[27] [29]
21	Andy Lee	[27] [28] [29]
22	E. Stewart Lee	[7]
23	Guy G. Lemieux	[22] [24] [25] [26]
24	Paul Leventis	[22] [27] [29]
25	Sandy Marquardt	[27] [29]
26	Cameron McClintock	[27] [29]
27	Ketan Padalia	[28] [29]
28	Ahmet N. Parlakbilek	[11]
29	Bruce Pedersen	[27] [28] [29]
30	Giles Powell	[27] [29]
31	Boris Ratchev	[28] [29]
32	Srinivas Reddy	[27] [29]
33	Jonathan Rose	[18] [20] [27] [29]
34	Rahul Saini	[28]
35	Jay Schleicher	[28] [29]
36	Kevin Stevens	[29]
37	Michael Stumm	[7] [9]
38	Brian W. Thomson	[2] [7]
39	Zvonko G. Vranesic	[9]
40	Qiang Wang	[19] [23]
41	Ron White	[9]
42	Daniel H. Wong	[14]
43	Chris Wysocki	[27]
44	Andy Gean Ye	[21]
45	Richard Yuan	[28] [29]
46	L. Louis Zhang	[23]

Colors in the list of coauthors