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Antonio García

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2008
25EEDiego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-Vallvey: Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. FPL 2008: 635-638
24EEAlberto Díaz, Antonio García, Pablo Gervás: User-centred versus system-centred evaluation of a personalization system. Inf. Process. Manage. 44(3): 1293-1307 (2008)
2007
23EEAntonio García, Carlos León, Iñigo Monedero, Jorge Ropero: A Precise Electrical Disturbance Generator for Neural Network Training with Real Level Output. CIARP 2007: 534-545
22EEEncarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz: Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. FPL 2007: 183-188
21EEDiego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo: Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. FPL 2007: 706-709
20EEEncarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz: IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. IEEE Trans. VLSI Syst. 15(5): 578-591 (2007)
2006
19EEEncarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse: IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL 2006: 1-6
2005
18 Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz: Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. FPL 2005: 531-534
17EEDaniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz: Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. PATMOS 2005: 657-665
16EEAlberto Díaz, Pablo Gervás, Antonio García: Evaluation of a System for Personalized Summarization of Web Contents. User Modeling 2005: 453-462
15EEJavier Ramírez, Uwe Meyer-Bäse, Antonio García: Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology. Journal of Circuits, Systems, and Computers 14(1): 165-177 (2005)
2004
14EELuis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz: Intellectual Property Protection for RNS Circuits on FPGAs. FPL 2004: 1139-1141
13EEUwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García: Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. FPL 2004: 384-393
12 Miguel A. Melgarejo, Carlos Andrés Peña-Reyes, Antonio García: Computational model and architectural proposal for a hardware type-2 fuzzy system. Neural Networks and Computational Intelligence 2004: 279-284
2003
11EEJavier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz: Design and Implementation of RNS-Based Adaptive Filters. FPL 2003: 1135-1138
10EEJavier Ramírez, Antonio García: A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation. Journal of Circuits, Systems, and Computers 12(1): 111- (2003)
9EEJavier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz: Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. VLSI Signal Processing 33(1-2): 171-190 (2003)
8EEJavier Ramírez, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García, Antonio Lloris-Ruíz: Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. VLSI Signal Processing 34(3): 227-237 (2003)
2002
7EEJavier Ramírez, Antonio García: U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. FPL 2002: 472-481
6EEUwe Meyer-Bäse, Javier Ramírez, Antonio García: Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. FPL 2002: 897-904
5EEDaniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz: A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. PATMOS 2002: 188-197
2001
4EEUwe Meyer-Bäse, Antonio García, Fred J. Taylor: Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. VLSI Signal Processing 28(1-2): 115-128 (2001)
2000
3EEJavier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz: Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. FPL 2000: 342-351
1999
2EEAntonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor: RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. ISCAS (1) 1999: 486-489
1 Antonio García, Antonio Lloris-Ruíz: A Look-Up Scheme for Scaling in the RNS. IEEE Trans. Computers 48(7): 748-751 (1999)

Coauthor Index

1Luis F. Capitan-Vallvey [25]
2Miguel A. Carvajal [25]
3Encarnación Castillo [14] [17] [18] [19] [20] [21] [22] [25]
4Alberto Díaz Esteban (Alberto Díaz) [16] [24]
5Pedro G. Fernández [3]
6Pablo Gervás (Pablo Gervás Gómez-Navarro) [16] [24]
7Daniel González [5] [17]
8Graham A. Jullien [5]
9Carlos León [23]
10Antonio Lloris-Ruíz [1] [2] [3] [5] [8] [9] [11] [14] [17] [18] [19] [20] [22]
11Antonio Martínez-Olmos [21]
12Miguel A. Melgarejo [12]
13Uwe Meyer-Bäse [2] [4] [6] [8] [9] [11] [13] [15] [18] [19] [20] [22]
14Iñigo Monedero [23]
15Diego P. Morales [21] [25]
16Alberto J. Palma [21] [25]
17Luis Parrilla [3] [5] [14] [17] [19] [20] [22]
18Carlos Andrés Peña-Reyes [12]
19Javier Ramírez [3] [5] [6] [7] [8] [9] [10] [11] [13] [15] [18]
20Suhasini Rao [13]
21Jorge Ropero [23]
22Fred J. Taylor [2] [4] [8] [9]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)