2008 |
25 | EE | Diego P. Morales,
Antonio García,
Alberto J. Palma,
Miguel A. Carvajal,
Encarnación Castillo,
Luis F. Capitan-Vallvey:
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.
FPL 2008: 635-638 |
24 | EE | Alberto Díaz,
Antonio García,
Pablo Gervás:
User-centred versus system-centred evaluation of a personalization system.
Inf. Process. Manage. 44(3): 1293-1307 (2008) |
2007 |
23 | EE | Antonio García,
Carlos León,
Iñigo Monedero,
Jorge Ropero:
A Precise Electrical Disturbance Generator for Neural Network Training with Real Level Output.
CIARP 2007: 534-545 |
22 | EE | Encarnación Castillo,
Luis Parrilla,
Antonio García,
Uwe Meyer-Bäse,
Antonio Lloris-Ruíz:
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
FPL 2007: 183-188 |
21 | EE | Diego P. Morales,
Antonio García,
Alberto J. Palma,
Antonio Martínez-Olmos,
Encarnación Castillo:
Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing.
FPL 2007: 706-709 |
20 | EE | Encarnación Castillo,
Uwe Meyer-Bäse,
Antonio García,
Luis Parrilla,
Antonio Lloris-Ruíz:
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.
IEEE Trans. VLSI Syst. 15(5): 578-591 (2007) |
2006 |
19 | EE | Encarnación Castillo,
Luis Parrilla,
Antonio García,
Antonio Lloris-Ruíz,
Uwe Meyer-Bäse:
IPP Watermarking Technique for IP Core Protection on FPL Devices.
FPL 2006: 1-6 |
2005 |
18 | | Antonio García,
Javier Ramírez,
Uwe Meyer-Bäse,
Encarnación Castillo,
Antonio Lloris-Ruíz:
Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks.
FPL 2005: 531-534 |
17 | EE | Daniel González,
Luis Parrilla,
Antonio García,
Encarnación Castillo,
Antonio Lloris-Ruíz:
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.
PATMOS 2005: 657-665 |
16 | EE | Alberto Díaz,
Pablo Gervás,
Antonio García:
Evaluation of a System for Personalized Summarization of Web Contents.
User Modeling 2005: 453-462 |
15 | EE | Javier Ramírez,
Uwe Meyer-Bäse,
Antonio García:
Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology.
Journal of Circuits, Systems, and Computers 14(1): 165-177 (2005) |
2004 |
14 | EE | Luis Parrilla,
Encarnación Castillo,
Antonio García,
Antonio Lloris-Ruíz:
Intellectual Property Protection for RNS Circuits on FPGAs.
FPL 2004: 1139-1141 |
13 | EE | Uwe Meyer-Bäse,
Suhasini Rao,
Javier Ramírez,
Antonio García:
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.
FPL 2004: 384-393 |
12 | | Miguel A. Melgarejo,
Carlos Andrés Peña-Reyes,
Antonio García:
Computational model and architectural proposal for a hardware type-2 fuzzy system.
Neural Networks and Computational Intelligence 2004: 279-284 |
2003 |
11 | EE | Javier Ramírez,
Uwe Meyer-Bäse,
Antonio García,
Antonio Lloris-Ruíz:
Design and Implementation of RNS-Based Adaptive Filters.
FPL 2003: 1135-1138 |
10 | EE | Javier Ramírez,
Antonio García:
A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation.
Journal of Circuits, Systems, and Computers 12(1): 111- (2003) |
9 | EE | Javier Ramírez,
Antonio García,
Uwe Meyer-Bäse,
Fred J. Taylor,
Antonio Lloris-Ruíz:
Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.
VLSI Signal Processing 33(1-2): 171-190 (2003) |
8 | EE | Javier Ramírez,
Uwe Meyer-Bäse,
Fred J. Taylor,
Antonio García,
Antonio Lloris-Ruíz:
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies.
VLSI Signal Processing 34(3): 227-237 (2003) |
2002 |
7 | EE | Javier Ramírez,
Antonio García:
U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation.
FPL 2002: 472-481 |
6 | EE | Uwe Meyer-Bäse,
Javier Ramírez,
Antonio García:
Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs.
FPL 2002: 897-904 |
5 | EE | Daniel González,
Antonio García,
Graham A. Jullien,
Javier Ramírez,
Luis Parrilla,
Antonio Lloris-Ruíz:
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems.
PATMOS 2002: 188-197 |
2001 |
4 | EE | Uwe Meyer-Bäse,
Antonio García,
Fred J. Taylor:
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.
VLSI Signal Processing 28(1-2): 115-128 (2001) |
2000 |
3 | EE | Javier Ramírez,
Antonio García,
Pedro G. Fernández,
Luis Parrilla,
Antonio Lloris-Ruíz:
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.
FPL 2000: 342-351 |
1999 |
2 | EE | Antonio García,
Uwe Meyer-Bäse,
Antonio Lloris-Ruíz,
Fred J. Taylor:
RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic.
ISCAS (1) 1999: 486-489 |
1 | | Antonio García,
Antonio Lloris-Ruíz:
A Look-Up Scheme for Scaling in the RNS.
IEEE Trans. Computers 48(7): 748-751 (1999) |