William P. Marnane

2009
28	EE	Brian Baldwin, Richard Moloney, Andrew Byrne, Gary McGuire, William P. Marnane: A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem. ARC 2009: 355-361
2008
27	EE	Maurice Keller, William P. Marnane: Energy Efficient Elliptic Curve Processor. PATMOS 2008: 287-296
2007
26	EE	Andrew Byrne, Nicolas Meloni, Francis M. Crowe, William P. Marnane, Arnaud Tisserand, Emanuel M. Popovici: SPA resistant Elliptic Curve Cryptosystem using Addition Chains. ITNG 2007: 995-1000
25	EE	Maurice Keller, William P. Marnane: Low Power Elliptic Curve Cryptography. PATMOS 2007: 310-319
24	EE	Robert P. McEvoy, Michael Tunstall, Colin C. Murphy, William P. Marnane: Differential Power Analysis of HMAC Based on SHA-2, and Countermeasures. WISA 2007: 317-332
23	EE	Maurice Keller, Robert Ronan, William P. Marnane, Colin C. Murphy: Hardware architectures for the Tate pairing over GF(2m). Computers & Electrical Engineering 33(5-6): 392-406 (2007)
22	EE	Tim Kerins, William P. Marnane, Emanuel M. Popovici: Versatile hardware architectures for GF(pm) arithmetic in public key cryptography. Integration 40(1): 28-35 (2007)
21	EE	María del Carmen Pérez, Jesús Ureña, Álvaro Hernández, Carlos De Marziani, Ana Jiménez, William P. Marnane: Hardware Implementation of an Efficient Correlator for Interleaved Complementary Sets of Sequences. J. UCS 13(3): 388-406 (2007)
20	EE	Andrew Byrne, Nicolas Meloni, Arnaud Tisserand, Emanuel M. Popovici, William P. Marnane: Comparison of Simple Power Analysis Attack Resistant Algorithms for an Elliptic Curve Cryptosystem. JCP 2(10): 52-62 (2007)
2006
19	EE	Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane: FPGA Implementation of a GF(2m) Tate Pairing Architecture. ARC 2006: 358-369
18	EE	María del Carmen Pérez, Jesús Ureña, Álvaro Hernández, Carlos De Marziani, A. Ochoa, William P. Marnane: FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences. FPL 2006: 1-4
17	EE	Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane: Optimisation of the SHA-2 Family of Hash Functions on FPGAs. ISVLSI 2006: 317-322
16	EE	Robert Ronan, Colm O'Eigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane: An Embedded Processor for a Pairing-Based Cryptosystem. ITNG 2006: 192-197
15		Stephen Faul, Gregor Gregorcic, Geraldine B. Boylan, William P. Marnane, Gordon Lightbody, Sean Connolly: Gaussian Process Modelling as an Indicator of Neonatal Seizure. SPPRA 2006: 177-182
2005
14	EE	Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto: Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. CHES 2005: 412-426
13		Maurice Keller, Tim Kerins, William P. Marnane: FPGA Implementation of a GF(24M) Multiplier for use in Pairing Based Cryptosystems. FPL 2005: 594-597
12	EE	Francis M. Crowe, Alan Daly, William P. Marnane: A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems. ITCC (1) 2005: 568-573
2004
11	EE	Tim Kerins, Emanuel M. Popovici, William P. Marnane: Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. FPL 2004: 74-83
10	EE	Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici: An FPGA implementation of a GF(p) ALU for encryption processors. Microprocessors and Microsystems 28(5-6): 253-260 (2004)
2003
9	EE	Alan Daly, William P. Marnane, Tim Kerins, Emanuel M. Popovici: Fast Modular Division for Application in ECC on Reconfigurable Logic. FPL 2003: 786-795
2002
8	EE	Alan Daly, William P. Marnane: Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. FPGA 2002: 40-49
7	EE	Tim Kerins, Emanuel M. Popovici, William P. Marnane, Patrick Fitzpatrick: Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2). FPL 2002: 750-759
2001
6	EE	Henrik Eriksson, Per Larsson-Edefors, William P. Marnane: A regular parallel multiplier which utilizes multiple carry-propagate adders. ISCAS (4) 2001: 166-169
2000
5	EE	Stephen J. Bellis, William P. Marnane: A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. FPL 2000: 485-494
1997
4	EE	Stephen J. Bellis, Peter J. Fish, William P. Marnane: Optimal Systolic Arrays for Real-time Implementation of the Modified Covariance Spectral Estimator. Parallel Algorithms Appl. 11(1-2): 71-96 (1997)
1995
3		William P. Marnane, C. N. Jordan, F. J. O'Reilly: Compiling Regular Arrays onto FPGAs. FPL 1995: 178-187
2	EE	William P. Marnane, W. R. Moore: Testing VLSI regular arrays. J. Electronic Testing 6(2): 153-177 (1995)
1992
1		Myles H. Capstick, William P. Marnane, Ronald Pethig: Biologic Computational Building Blocks. IEEE Computer 25(11): 22-29 (1992)

Coauthor Index

1	Brian Baldwin	[28]
2	Paulo S. L. M. Barreto	[14]
3	Stephen J. Bellis	[4] [5]
4	Geraldine B. Boylan	[15]
5	Andrew Byrne	[20] [26] [28]
6	Myles H. Capstick	[1]
7	Sean Connolly	[15]
8	Francis M. Crowe	[12] [17] [19] [26]
9	Alan Daly	[8] [9] [10] [12]
10	Henrik Eriksson	[6]
11	Stephen Faul	[15]
12	Peter J. Fish	[4]
13	Patrick Fitzpatrick	[7]
14	Gregor Gregorcic	[15]
15	Álvaro Hernández	[18] [21]
16	Ana Jiménez	[21]
17	C. N. Jordan	[3]
18	Maurice Keller	[13] [19] [23] [25] [27]
19	Tim Kerins	[7] [9] [10] [11] [13] [14] [16] [19] [22]
20	Per Larsson-Edefors	[6]
21	Gordon Lightbody	[15]
22	Carlos De Marziani	[18] [21]
23	Robert P. McEvoy	[17] [24]
24	Gary McGuire	[28]
25	Nicolas Meloni	[20] [26]
26	Richard Moloney	[28]
27	W. R. Moore	[2]
28	Colin C. Murphy	[16] [17] [23] [24]
29	Colm O'Eigeartaigh	[16]
30	F. J. O'Reilly	[3]
31	A. Ochoa	[18]
32	María del Carmen Pérez	[18] [21]
33	Ronald Pethig	[1]
34	Emanuel M. Popovici	[7] [9] [10] [11] [14] [20] [22] [26]
35	Robert Ronan	[16] [23]
36	Michael Scott	[16]
37	Arnaud Tisserand	[20] [26]
38	Michael Tunstall	[24]
39	Jesús Ureña	[18] [21]

Colors in the list of coauthors