2004 |
5 | EE | Hideharu Amano,
Takeshi Inuo,
Hirokazu Kami,
Taro Fujii,
Masayasu Suzuki:
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
FPL 2004: 464-473 |
2001 |
4 | EE | Tsukasa Yamauchi,
Shogo Nakaya,
Takeshi Inuo,
Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW.
FPL 2001: 618-622 |
2000 |
3 | EE | Tsukasa Yamauchi,
Shogo Nakaya,
Takeshi Inuo,
Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW.
FCCM 2000: 281-282 |
1998 |
2 | | Hidenori Sakanashi,
Mehrdad Salami,
Masaya Iwata,
Shogo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression.
AAAI/IAAI 1998: 486-491 |
1 | EE | Isamu Kajitani,
Tsutomu Hoshino,
Daisuke Nishikawa,
Hiroshi Yokoi,
Shougo Nakaya,
Tsukasa Yamauchi,
Takeshi Inuo,
Nobuki Kajihara,
Masaya Iwata,
Didier Keymeulen,
Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI.
ICES 1998: 1-12 |