Richard Yuan

2006
4	EE	Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan: Efficient SAT-based Boolean matching for FPGA technology mapping. DAC 2006: 466-471
3	EE	Michael Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo: A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum 2006: 64-69
2005
2	EE	David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose: The Stratix II logic and routing architecture. FPGA 2005: 14-20
2004
1	EE	Michael Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini: Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144

Coauthor Index

1	Elias Ahmed	[2]
2	Gregg Baeckler	[1] [2] [3] [4]
3	Vaughn Betz	[2]
4	Mark Bourgeault	[1] [2]
5	David Cashman	[2]
6	Sammy Cheung	[3]
7	Kar Keng Chua	[3]
8	Richard Cliff	[2]
9	David R. Galloway	[2]
10	Michael Hutton (Michael D. Hutton, Mike Hutton)	[1] [2] [3]
11	Sinan Kaptanoglu	[1]
12	Henry Kim	[1]
13	Christopher Lane	[2]
14	Andy Lee	[1] [2]
15	Paul Leventis	[2]
16	David M. Lewis	[1] [2]
17	Sandy Marquardt	[2]
18	Cameron McClintock	[2]
19	Ketan Padalia	[1] [2]
20	Bruce Pedersen	[1] [2]
21	Hee Kong Phoo	[3]
22	Giles Powell	[2]
23	Boris Ratchev	[1] [2]
24	Srinivas Reddy	[2]
25	Jonathan Rose	[2]
26	Sean Safarpour	[4]
27	Rahul Saini	[1]
28	Jay Schleicher	[1] [2] [3]
29	Kevin Stevens	[2]
30	Andreas G. Veneris	[4]