| 2006 |
|---|
| 6 | EE | Nicola Campregher,
Peter Y. K. Cheung,
George A. Constantinides,
Milan Vasilko:
Yield enhancements of design-specific FPGAs.
FPGA 2006: 93-100 |
| 5 | EE | Nicola Campregher,
Peter Y. K. Cheung,
George A. Constantinides,
Milan Vasilko:
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs.
FPL 2006: 1-6 |
| 2005 |
|---|
| 4 | EE | Nicola Campregher,
Peter Y. K. Cheung,
George A. Constantinides,
Milan Vasilko:
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.
FPGA 2005: 138-148 |
| 3 | | Nicola Campregher,
Peter Y. K. Cheung,
George A. Constantinides,
Milan Vasilko:
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.
FPL 2005: 409-414 |
| 2 | | Nicola Campregher:
FPGA Interconnect Fault tolerance.
FPL 2005: 725-726 |
| 2004 |
|---|
| 1 | EE | Nicola Campregher,
Peter Y. K. Cheung,
Milan Vasilko:
BIST Based Interconnect Fault Location for FPGAs.
FPL 2004: 322-332 |
