Julio Villalba

2008
29	EE	Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata: New SIMD instructions set for image processing applications enhancement. ICIP 2008: 1396-1399
28	EE	Elisardo Antelo, Julio Villalba, Emilio L. Zapata: A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers 57(3): 404-417 (2008)
27	EE	Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata: Pipelined Architecture for Additive Range Reduction. Signal Processing Systems 53(1-2): 103-112 (2008)
2007
26	EE	Julio Villalba, Javier Hormigo, Tomás Lang: Improving the Throughput of On-line Addition for Data Streams. ASAP 2007: 272-277
2006
25	EE	Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata: Pipelined Range Reduction for Floating Point Numbers. ASAP 2006: 145-152
24	EE	Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata: Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL 2006: 1-4
23	EE	Julio Villalba, Tomás Lang, Mario A. González: Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. IEEE Trans. Computers 55(3): 254-267 (2006)
22	EE	Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata: SAD computation based on online arithmetic for motion estimation. Microprocessors and Microsystems 30(5): 250-258 (2006)
2005
21	EE	Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata: On-line Multioperand Addition Based on On-line Full Adders. ASAP 2005: 322-327
20	EE	Elisardo Antelo, Julio Villalba: Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic 2005: 280-287
2004
19	EE	Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides: Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL 2004: 986-990
18	EE	Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata: Evaluation of Elementary Functions Using Multimedia Features. IPDPS 2004
17	EE	Javier Hormigo, Julio Villalba, Emilio L. Zapata: CORDIC Processor for Variable-Precision Interval Arithmetic. VLSI Signal Processing 37(1): 21-39 (2004)
2002
16	EE	Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata: Polynomial Evaluation on Multimedia Processors. ASAP 2002: 265-
2000
15	EE	Javier Hormigo, Julio Villalba, Michael J. Schulte: A Hardware Algorithm for Variable-Precision Logarithm. ASAP 2000: 215-224
14		Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata: MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) 2000: 1383-1386
1999
13	EE	Javier Hormigo, Julio Villalba, Emilio L. Zapata: Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO 1999: 1063-1066
12	EE	Javier Hormigo, Julio Villalba, Emilio L. Zapata: Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 1999: 186-193
1998
11	EE	Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring CORDIC Algorithm and Architectures. VLSI Signal Processing 19(2): 127-147 (1998)
10	EE	Julio Villalba, Tomás Lang, Emilio L. Zapata: Parallel Compensation of Scale Factor for the CORDIC Algorithm. VLSI Signal Processing 19(3): 227-241 (1998)
1997
9	EE	Julio Villalba, Tomás Lang: Low latency word serial CORDIC. ASAP 1997: 124-131
8		Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata: High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers 46(8): 855-870 (1997)
1996
7	EE	Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP 1996: 55-64
6		Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata: High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II 1996: 155-164
5	EE	Javier D. Bruguera, Nicolas Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata: Cordic based parallel/pipelined architecture for the Hough transform. VLSI Signal Processing 12(3): 207-221 (1996)
1995
4	EE	Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257
3	EE	Julio Villalba, J. A. Hidalgo, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera: CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP 1995: 258-269
2	EE	Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata: Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic 1995: 172-179
1	EE	Nicolas Guil, Julio Villalba, Emilio L. Zapata: A fast Hough transform for segment detection. IEEE Transactions on Image Processing 4(11): 1541-1548 (1995)

Coauthor Index

1	Elisardo Antelo	[2] [3] [4] [6] [7] [8] [11] [20] [28]
2	J. C. Arrabal	[7]
3	Gerardo Bandera	[16] [18]
4	Ignacio Benavides	[19] [22] [24]
5	Javier D. Bruguera	[2] [3] [4] [5] [6] [7] [8] [11]
6	Mario A. González	[14] [16] [18] [23]
7	J. A. Hidalgo	[3]
8	Javier Hormigo	[12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [24] [25] [26] [27] [29]
9	Francisco J. Jaime	[25] [27] [29]
10	Tomás Lang	[5] [6] [9] [10] [23] [26]
11	Nicolás Guil Mata (Nicolas Guil)	[1] [5]
12	Joaquín Olivares	[19] [22] [24]
13	Roberto R. Osorio	[4]
14	Jose M. Prades	[21]
15	Michael J. Schulte	[15]
16	Emilio L. Zapata	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12] [13] [14] [16] [17] [18] [21] [22] [24] [25] [27] [28] [29]