2007 |
29 | | Takayoshi Shimazu,
Shin'ichi Wakabayashi,
Shinobu Nagayama:
A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning.
PDPTA 2007: 801-807 |
2006 |
28 | EE | Tomotake Nakamura,
Yoko Kamidoi,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A Decision Method of Attribute Importance for Classification by Outlier Detection.
ICDE Workshops 2006: 120 |
2005 |
27 | | Shin'ichi Wakabayashi,
Kenji Kikuchi:
Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs.
FPT 2005: 69-76 |
26 | EE | Tomotake Nakamura,
Yoko Kamidoi,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
Feature Extraction of Clusters Based on FlexDice.
ICDE Workshops 2005: 1126 |
25 | EE | Takeshi Fushimi,
Yoko Kamidoi,
Shin'ichi Wakabayashi:
An Algorithm for Computing Global-Based Outlier Degrees on Data Sets.
ICDE Workshops 2005: 1224 |
24 | EE | Tomotake Nakamura,
Yoko Kamidoi,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A Clustering Method Using an Irregular Size Cell Graph.
RIDE 2005: 19-26 |
2004 |
23 | EE | Shin'ichi Wakabayashi,
Kenji Kikuchi:
An Instance-Specific Hardware Algorithm for Finding a Maximum Clique.
FPL 2004: 516-525 |
2002 |
22 | EE | Yoko Kamidoi,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A Divide-and-Conquer Approach to the Minimum k-Way Cut Problem.
Algorithmica 32(2): 262-276 (2002) |
21 | EE | Shigeki Takekawa,
Shin'ichi Wakabayashi,
Tetsushi Koide:
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time.
Systems and Computers in Japan 33(12): 87-96 (2002) |
2001 |
20 | EE | Koichi Hatta,
Shin'ichi Wakabayashi,
Tetsushi Koide:
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual.
Systems and Computers in Japan 32(1): 29-37 (2001) |
2000 |
19 | EE | Shin'ichi Wakabayashi,
Tetsushi Koide,
Nayoshi Toshine,
Masataka Yamane,
Hajime Ueno:
Genetic algorithm accelerator GAA-II.
ASP-DAC 2000: 9-10 |
18 | EE | Takahiro Deguchi,
Tetsushi Koide,
Shin'ichi Wakabayashi:
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer.
ASP-DAC 2000: 99-104 |
1999 |
17 | EE | Koichi Hatta,
Shin'ichi Wakabayashi,
Tetsushi Koide:
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair.
ASP-DAC 1999: 181-184 |
16 | EE | Shin'ichi Wakabayashi,
Tetsushi Koide,
Naoyoshi Toshine,
Mutsuaki Goto,
Yoshikatsu Nakayama,
Koichi Hatta:
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.
ASP-DAC 1999: 37-40 |
15 | EE | Tetsushi Koide,
Shin'ichi Wakabayashi:
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.
Integration 27(1): 57-76 (1999) |
1998 |
14 | | Tetsushi Koide,
Shin'ichi Wakabayashi:
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout.
ASP-DAC 1998: 577-583 |
13 | EE | Koichi Hatta,
Masashige Suzuki,
Shin'ichi Wakabayashi,
Tetsushi Koide:
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm.
PPSN 1998: 1028-1037 |
1997 |
12 | EE | Tetsushi Koide,
Shin'ichi Wakabayashi,
Mitsuhiro Ono,
Yutaka Nishimaru,
Noriyoshi Yoshida:
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs.
Integration 24(1): 53-77 (1997) |
1996 |
11 | EE | Tetsushi Koide,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
Pin assignment with global routing for VLSI building block layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1575-1583 (1996) |
10 | EE | Tetsushi Koide,
Masahiro Tsuchiya,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A three-layer over-the-cell multi-channel router for a new cell model.
Integration 21(3): 171-189 (1996) |
1995 |
9 | EE | Tetsushi Koide,
Mitsuhiro Ono,
Shin'ichi Wakabayashi,
Yutaka Nishimaru:
A new performance driven placement method with the Elmore delay model for row based VLSIs.
ASP-DAC 1995 |
8 | EE | Yoshinori Katsura,
Tetsushi Koide,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A new system partitioning method under performance and physical constraints for multi-chip modules.
ASP-DAC 1995 |
7 | EE | Masahiro Tsuchiya,
Tetsushi Koide,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A three-layer over-cell multi-channel routing method for a new cell model.
ASP-DAC 1995 |
6 | | Toshihiro Nakaoa,
Shin'ichi Wakabayashi,
Tetsushi Koide,
Noriyoshi Yoshida:
A Verification Algorithm for Logic Circuits with Internal Variables.
ISCAS 1995: 1920-1923 |
5 | | Tetsuya Miyoshi,
Shin'ichi Wakabayashi,
Tetsushi Koide,
Noriyoshi Yoshida:
An MCM Routing Algorithm Considering Crosstalk.
ISCAS 1995: 211-214 |
1994 |
4 | | Tetsushi Koide,
Yoshinori Katsura,
Katsumi Yamatani,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
A Floorplanning Method with Topological Constraint Manipulation.
ISCAS 1994: 165-168 |
3 | | Yoko Kamidoi,
Shin'ichi Wakabayashi,
Noriyoshi Yoshida:
On Three-Way Graph Partitioning.
ISCAS 1994: 173-176 |
2 | | Shin'ichi Wakabayashi,
Kazunori Isomoto,
Tetsushi Koide,
Noriyoshi Yoshida:
A Systolic Graph Partitioning Algorithm for VLSI Design.
ISCAS 1994: 225-228 |
1993 |
1 | | Shin'ichi Wakabayashi,
Hiroshi Kusumoto,
Hideki Mishima,
Tetsushi Koide,
Noriyoshi Yoshida:
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints.
ISCAS 1993: 2059-2062 |