| |
| 2006 | ||
|---|---|---|
| 4 | EE | Rawat Siripokarpirom: Platform Development for Run-Time Reconfigurable Co-Emulation. IEEE International Workshop on Rapid System Prototyping 2006: 179-185 |
| 2005 | ||
| 3 | Rawat Siripokarpirom: A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test. FPL 2005: 505-508 | |
| 2004 | ||
| 2 | EE | Rawat Siripokarpirom: Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs. FPL 2004: 700-709 |
| 1 | EE | Rawat Siripokarpirom, Friedrich Mayer-Lindenberg: Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards. IEEE International Workshop on Rapid System Prototyping 2004: 96-102 |
| 1 | Friedrich Mayer-Lindenberg | [1] |