2004 |
10 | EE | Jason Helge Anderson,
Sudip Nag,
Kamal Chaudhary,
Sandor Kalman,
Chari Madabhushi,
Paul Cheng:
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.
FPL 2004: 168-178 |
1999 |
9 | EE | Sudip Nag,
Kamal Chaudhary:
Post-Placement Residual-Overlap Removal with Minimal Movement.
DATE 1999: 581-586 |
1995 |
8 | EE | Kamal Chaudhary,
Massoud Pedram:
Computing the area versus delay trade-off curves in technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1480-1489 (1995) |
7 | EE | Akira Onozawa,
Kamal Chaudhary,
Ernest S. Kuh:
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 707-719 (1995) |
1994 |
6 | EE | Sasan Iman,
Massoud Pedram,
Kamal Chaudhary:
Technology Mapping Using Fuzzy Logic.
DAC 1994: 333-338 |
1993 |
5 | EE | Kamal Chaudhary,
Akira Onozawa,
Ernest S. Kuh:
A spacing algorithm for performance enhancement and cross-talk reduction.
ICCAD 1993: 697-702 |
1992 |
4 | EE | Kamal Chaudhary,
Massoud Pedram:
A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints.
DAC 1992: 492-498 |
1991 |
3 | | Arvind Srinivasan,
Kamal Chaudhary,
Ernest S. Kuh:
RITUAL: Performance Driven Placement Algorithm for Small Cell ICs.
ICCAD 1991: 48-51 |
2 | | Massoud Pedram,
Kamal Chaudhary,
Ernest S. Kuh:
I/O Pad Assignment Based on the Circuit Structure.
ICCD 1991: 314-318 |
1 | EE | Kamal Chaudhary,
Peter Robinson:
Channel routing by sorting.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 754-760 (1991) |