2008 |
19 | EE | Slavisa Jovanovic,
Camel Tanougast,
Serge Weber:
A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems.
ARC 2008: 159-170 |
18 | EE | Slavisa Jovanovic,
Camel Tanougast,
Serge Weber:
A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems.
ASAP 2008: 61-66 |
17 | EE | Camel Tanougast,
Serge Weber,
Gilles Millerioux,
Jamal Daafouz,
Ahmed Bouridane:
VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher.
DELTA 2008: 386-389 |
16 | EE | Ting Liu,
Camel Tanougast,
Serge Weber:
A framework of architectural synthesis for dynamically reconfigurable FPGAs.
SoCC 2008: 283-286 |
2007 |
15 | EE | Ould-cheikh Mourad,
Si-Mohamed Lotfy,
Noureddine Mehallegue,
Ahmed Bouridane,
Camel Tanougast:
AES Embedded Hardware Implementation.
AHS 2007: 103-109 |
14 | EE | Camel Tanougast,
Serge Weber,
Gilles Millerioux,
Ahmed Bouridane,
Jamal Daafouz:
An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance.
AHS 2007: 110-118 |
13 | EE | Slavisa Jovanovic,
Camel Tanougast,
Serge Weber:
A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems.
AHS 2007: 358-364 |
12 | EE | Slavisa Jovanovic,
Camel Tanougast,
Christophe Bobda,
Serge Weber:
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs.
FPL 2007: 753-756 |
11 | | Slavisa Jovanovic,
Camel Tanougast,
Christophe Bobda,
Serge Weber:
A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs.
ReCoSoC 2007: 98-105 |
10 | EE | Oscar Pérez,
Yves Berviller,
Camel Tanougast,
Serge Weber:
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation.
J. UCS 13(3): 349-362 (2007) |
2005 |
9 | | Michael Janiaut,
Camel Tanougast,
Hassan Rabah,
Yves Berviller,
Christian Mannino,
Serge Weber:
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
FPL 2005: 386-390 |
2004 |
8 | | Christian Mannino,
Hassan Rabah,
Camel Tanougast,
Yves Berviller,
Michael Janiaut,
Serge Weber:
FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T.
ESA/VLSI 2004: 606-610 |
7 | EE | Christian Mannino,
Hassan Rabah,
Camel Tanougast,
Yves Berviller,
Michael Janiaut,
Serge Weber:
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.
FPL 2004: 1027-1031 |
6 | EE | Camel Tanougast,
Yves Berviller,
Christian Mannino,
Hassan Rabah,
Michael Janiaut,
Serge Weber:
SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation.
IEEE International Workshop on Rapid System Prototyping 2004: 157-163 |
2003 |
5 | EE | Camel Tanougast,
Yves Berviller,
Philippe Brunet,
Serge Weber:
Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design.
IPDPS 2003: 178 |
4 | EE | Philippe Brunet,
Camel Tanougast,
Yves Berviller,
Serge Weber:
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design.
IWSOC 2003: 106-111 |
3 | EE | Camel Tanougast,
Yves Berviller,
Philippe Brunet,
Serge Weber,
Hassan Rabah:
Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system.
Microprocessors and Microsystems 27(3): 115-130 (2003) |
2 | EE | Hassan Rabah,
Hervé Mathias,
Serge Weber,
Eril Mozef,
Camel Tanougast:
Linear array processors with multiple access modes memory for real-time image processing.
Real-Time Imaging 9(3): 205-213 (2003) |
2000 |
1 | EE | Camel Tanougast,
Yves Berviller,
Serge Weber:
Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation.
IPDPS Workshops 2000: 959-965 |