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Encarnación Castillo

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2008
8EEDiego P. Morales, Antonio García, Alberto J. Palma, Miguel A. Carvajal, Encarnación Castillo, Luis F. Capitan-Vallvey: Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. FPL 2008: 635-638
2007
7EEEncarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz: Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. FPL 2007: 183-188
6EEDiego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo: Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. FPL 2007: 706-709
5EEEncarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz: IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. IEEE Trans. VLSI Syst. 15(5): 578-591 (2007)
2006
4EEEncarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse: IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL 2006: 1-6
2005
3 Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz: Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. FPL 2005: 531-534
2EEDaniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz: Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. PATMOS 2005: 657-665
2004
1EELuis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz: Intellectual Property Protection for RNS Circuits on FPGAs. FPL 2004: 1139-1141

Coauthor Index

1Luis F. Capitan-Vallvey [8]
2Miguel A. Carvajal [8]
3Antonio García [1] [2] [3] [4] [5] [6] [7] [8]
4Daniel González [2]
5Antonio Lloris-Ruíz [1] [2] [3] [4] [5] [7]
6Antonio Martínez-Olmos [6]
7Uwe Meyer-Bäse [3] [4] [5] [7]
8Diego P. Morales [6] [8]
9Alberto J. Palma [6] [8]
10Luis Parrilla [1] [2] [4] [5] [7]
11Javier Ramírez [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)