| 2008 |
|---|
| 8 | EE | Diego P. Morales,
Antonio García,
Alberto J. Palma,
Miguel A. Carvajal,
Encarnación Castillo,
Luis F. Capitan-Vallvey:
Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.
FPL 2008: 635-638 |
| 2007 |
|---|
| 7 | EE | Encarnación Castillo,
Luis Parrilla,
Antonio García,
Uwe Meyer-Bäse,
Antonio Lloris-Ruíz:
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
FPL 2007: 183-188 |
| 6 | EE | Diego P. Morales,
Antonio García,
Alberto J. Palma,
Antonio Martínez-Olmos,
Encarnación Castillo:
Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing.
FPL 2007: 706-709 |
| 5 | EE | Encarnación Castillo,
Uwe Meyer-Bäse,
Antonio García,
Luis Parrilla,
Antonio Lloris-Ruíz:
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.
IEEE Trans. VLSI Syst. 15(5): 578-591 (2007) |
| 2006 |
|---|
| 4 | EE | Encarnación Castillo,
Luis Parrilla,
Antonio García,
Antonio Lloris-Ruíz,
Uwe Meyer-Bäse:
IPP Watermarking Technique for IP Core Protection on FPL Devices.
FPL 2006: 1-6 |
| 2005 |
|---|
| 3 | | Antonio García,
Javier Ramírez,
Uwe Meyer-Bäse,
Encarnación Castillo,
Antonio Lloris-Ruíz:
Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks.
FPL 2005: 531-534 |
| 2 | EE | Daniel González,
Luis Parrilla,
Antonio García,
Encarnación Castillo,
Antonio Lloris-Ruíz:
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.
PATMOS 2005: 657-665 |
| 2004 |
|---|
| 1 | EE | Luis Parrilla,
Encarnación Castillo,
Antonio García,
Antonio Lloris-Ruíz:
Intellectual Property Protection for RNS Circuits on FPGAs.
FPL 2004: 1139-1141 |
