Rafael Gadea Gironés

2008
14	EE	Agustín Ramirez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero: A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. Microprocessors and Microsystems - Embedded Hardware Design 32(1): 33-44 (2008)
2007
13	EE	Fernando Mateo, Ramón José Aliaga, Jorge Daniel Martínez, José María Monzó, Rafael Gadea Gironés: Incidence Position Estimation in a PET Detector Using a Discretized Positioning Circuit and Neural Networks. IWANN 2007: 684-691
2006
12	EE	Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés: A Novel FPGA Architecture of a 2-D Wavelet Transform. VLSI Signal Processing 42(3): 273-284 (2006)
2005
11	EE	Joaquín Cerdá, Rafael Gadea Gironés, Jorge Daniel Martínez, Angel Sebastia: A Tool for Implementing and Exploring SBM Models: Universal 1D Invertible Cellular Automata. IWINAC (1) 2005: 279-289
10	EE	Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés: FPGA Implementation of a Pipelined On-Line Backpropagation. VLSI Signal Processing 40(2): 189-213 (2005)
2004
9	EE	Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer: FPGA Custom DSP for ECG Signal Analysis and Compression. FPL 2004: 954-958
8	EE	Joaquín Cerdá-Boluda, Oscar Amoraga-Lechiguero, Ruben Torres-Curado, Rafael Gadea Gironés, Angel Sebastià-Cortés: FPGA Implementations of the RNR Cellular Automata to Model Electrostatic Field. VECPAR 2004: 382-395
7	EE	Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco Ballester, Marcos Martínez Peiró: Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocessors and Microsystems 28(9): 509-518 (2004)
2003
6	EE	Rafael Gadea Gironés, Agustín Ramirez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero: FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. FPL 2003: 1016-1019
5	EE	Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia: On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. FPL 2003: 776-785
4	EE	Joaquín Cerdá, Rafael Gadea Gironés, Guillermo Payá Vayá: Implementing a Margolus Neighborhood Cellular Automata on a FPGA. IWANN (2) 2003: 121-128
2000
3	EE	Rafael Gadea Gironés, Vicente Herrero, Angel Sebastia, Antonio Mocholí Salcedo: The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. FPL 2000: 785-788
2	EE	Rafael Gadea Gironés, Joaquín Cerdá, Francisco Ballester, Antonio Mocholí Salcedo: Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS 2000: 225-230
1999
1		Rafael Gadea Gironés, Antonio Mocholí Salcedo: Forward-Backward Parallelism in On-Line Backpropagation. IWANN (2) 1999: 157-165

Coauthor Index

1	Ramón José Aliaga	[13]
2	Oscar Amoraga-Lechiguero	[8]
3	Francisco Ballester	[2] [7] [9]
4	J. Belenguer	[9]
5	Joaquín Cerdá	[2] [4] [5] [11]
6	Joaquín Cerdá-Boluda	[6] [8] [10]
7	Ricardo José Colom-Palero	[6] [7] [9] [10] [12] [14]
8	Vicente Herrero	[3] [5]
9	Jorge Daniel Martínez	[11] [13]
10	Fernando Mateo	[13]
11	José María Monzó	[13]
12	Marcos Martínez Peiró	[7] [9]
13	Agustín Ramirez-Agundis	[6] [14]
14	Antonio Mocholí Salcedo	[1] [2] [3]
15	Angel Sebastia	[3] [5] [11]
16	Angel Sebastià-Cortés	[8] [10] [12]
17	Ruben Torres-Curado	[8]
18	Guillermo Payá Vayá	[4] [9]