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| 2004 | ||
|---|---|---|
| 2 | EE | Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng: Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. FPL 2004: 168-178 |
| 2000 | ||
| 1 | EE | Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman: A Placement Algorithm for FPGA Designs with Multiple I/O Standards. FPL 2000: 211-220 |
| 1 | Jason Helge Anderson | [1] [2] |
| 2 | Kamal Chaudhary | [2] |
| 3 | Paul Cheng | [2] |
| 4 | Rajeev Jayaraman | [1] |
| 5 | Sandor Kalman | [2] |
| 6 | Sudip Nag | [1] [2] |
| 7 | Jim Saunders | [1] |