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K. Tatas
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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24 | EE | Konstantinos Tatas, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, Stephan Wong: Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs. Parallel Processing Letters 18(2): 291-306 (2008) |
2007 | ||
23 | EE | Konstantinos Tatas, George Koutroumpezis, Dimitrios Soudris, Adonios Thanailakis: Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications. Integration 40(2): 74-93 (2007) |
2006 | ||
22 | EE | K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis: A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224 |
21 | EE | Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006 |
20 | EE | Nikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors. VLSI Signal Processing 44(1-2): 153-171 (2006) |
2005 | ||
19 | EE | Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis: AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4 |
18 | K. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661 | |
17 | EE | K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005 |
16 | EE | Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos: A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Transactions 88-D(7): 1369-1380 (2005) |
15 | EE | Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms. J. Embedded Computing 1(3): 353-362 (2005) |
14 | EE | Konstantinos Tatas, Dimitrios Soudris, D. Siomos, Adonios Thanailakis: A Novel Division Algorithm and Architectures for Parallel and Sequential Processing. Journal of Circuits, Systems, and Computers 14(2): 281-296 (2005) |
13 | EE | Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris: A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. Microprocessors and Microsystems 29(6): 247-259 (2005) |
2004 | ||
12 | EE | K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118 |
11 | EE | Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis: An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004 |
10 | EE | Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis: A reusable IP FFT core for DSP applications. ISCAS (3) 2004: 621-624 |
2003 | ||
9 | EE | Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035 |
8 | EE | Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis: A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. ISCAS (5) 2003: 129-132 |
7 | EE | Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas: Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439 |
6 | EE | Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis: FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616 |
5 | EE | Konstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis: Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms. Real-Time Imaging 9(6): 371-386 (2003) |
2002 | ||
4 | EE | George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis: Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. FPL 2002: 1027-1036 |
2001 | ||
3 | EE | Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis: Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731 |
2 | EE | Konstantinos Tatas, Antonios Argyriou, Minas Dasygenis, Dimitrios Soudris, Nikolaos D. Zervas: Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. ISQED 2001: 456-461 |
2000 | ||
1 | EE | Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254 |