| 2008 |
|---|
| 14 | EE | Cesar Torres-Huitzil,
Bernard Girau:
Implementation of Central Pattern Generator in an FPGA-Based Embedded System.
ICANN (2) 2008: 179-187 |
| 13 | EE | Cesar Torres-Huitzil,
Bernard Girau,
Miguel Arias-Estrada:
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity.
ICANN (2) 2008: 188-197 |
| 2007 |
|---|
| 12 | EE | Cesar Torres-Huitzil,
Bernard Girau,
Adrien Gauffriau:
Hardware/Software Codesign for Embedded Implementation of Neural Networks.
ARC 2007: 167-178 |
| 11 | EE | Bernard Girau,
Cesar Torres-Huitzil:
Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation.
Neurocomputing 70(7-9): 1186-1197 (2007) |
| 2006 |
|---|
| 10 | EE | Bernard Girau,
Cesar Torres-Huitzil:
FPGA implementation of an integrate-and-fire LEGION model for image segmentation.
ESANN 2006: 173-178 |
| 9 | EE | Cesar Torres-Huitzil:
Area-Efficient Implementation of a Pulse-Mode Neuron Model.
FPL 2006: 1-4 |
| 8 | EE | Cesar Torres-Huitzil:
A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks.
ICONIP (3) 2006: 1150-1159 |
| 2005 |
|---|
| 7 | | Cesar Torres-Huitzil,
Bernard Girau:
FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception.
FPT 2005: 259-266 |
| 6 | EE | Cesar Torres-Huitzil,
Bernard Girau,
Claudio Castellanos Sánchez:
On-chip visual perception of motion: A bio-inspired connectionist model on FPGA.
Neural Networks 18(5-6): 557-565 (2005) |
| 2004 |
|---|
| 5 | EE | Santos López-Estrada,
René Cumplido-Parra,
Cesar Torres-Huitzil:
A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing.
ENC 2004: 108-115 |
| 4 | EE | Cesar Torres-Huitzil,
René Cumplido-Parra,
Santos López-Estrada:
Design and Implementation of a CFAR Processor for Target Detection.
FPL 2004: 943-947 |
| 3 | EE | Cesar Torres-Huitzil,
Miguel Arias-Estrada:
Real-time image processing with a compact FPGA-based systolic architecture.
Real-Time Imaging 10(3): 177-187 (2004) |
| 2003 |
|---|
| 2 | EE | Cesar Torres-Huitzil,
Miguel Arias-Estrada:
Configurable Hardware Architecture for Real-Time Window-Based Image Processing.
FPL 2003: 1008-1011 |
| 2000 |
|---|
| 1 | EE | Cesar Torres-Huitzil,
Miguel Arias-Estrada:
An FPGA Architecture for High Speed Edge and Corner Detection.
CAMP 2000: 112-116 |
