Brian F. Veale

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6EENick A. Mould, Brian F. Veale, John K. Antonio, Monte P. Tull, John R. Junger: Design of steering vectors for dynamically reconfigurable architectures. IPDPS 2008: 1-8
5EENick A. Mould, Brian F. Veale, Monte P. Tull, John K. Antonio: Dynamic configuration steering for a reconfigurable superscalar processor. IPDPS 2006
4EEBrian F. Veale, John K. Antonio, Monte P. Tull, S. A. Jones: Selection of instruction set extensions for an FPGA embedded processor core. IPDPS 2006
3EEBrian F. Veale, John K. Antonio, Monte P. Tull: Configuration Steering for a Reconfigurable Superscalar Processor. IPDPS 2005
2EEBrian F. Veale, John K. Antonio, Monte P. Tull: Code Re-ordering for a Class of Reconfigurable Microprocessors. FPL 2004: 1170
1EETimothy Osmulski, Jeffrey T. Muehring, Brian F. Veale, Jack M. West, Hongping Li, Sirirut Vanichayobon, Seok-Hyun Ko, John K. Antonio, Sudarshan K. Dhall: A Probabilistic Power Prediction Tool for the Xilinx 4000-Series FPGA. IPDPS Workshops 2000: 776-783

Coauthor Index

1John K. Antonio [1] [2] [3] [4] [5] [6]
2Sudarshan K. Dhall [1]
3S. A. Jones [4]
4John R. Junger [6]
5Seok-Hyun Ko [1]
6Hongping Li [1]
7Nick A. Mould [5] [6]
8Jeffrey T. Muehring [1]
9Timothy Osmulski [1]
10Monte P. Tull [2] [3] [4] [5] [6]
11Sirirut Vanichayobon [1]
12Jack M. West [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)