| 2008 |
|---|
| 11 | EE | Ana Antunes,
Fernando Morgado Dias,
Jose Antonio Vieira,
Alexandre Mota:
A neuro-fuzzy delay compensator for distributed control systems.
ETFA 2008: 1088-1091 |
| 10 | EE | Ana Antunes,
Fernando Morgado Dias,
Alexandre Mota:
A neural network delay compensator for networked control systems.
ETFA 2008: 1271-1276 |
| 9 | EE | Ana Antunes,
Fernando Morgado Dias,
Alexandre Mota:
A Neural Model for Delay Correction in a Distributed Control System.
ICANN (2) 2008: 11-20 |
| 8 | EE | Fernando Morgado Dias,
Ana Antunes:
Fault Tolerance Improvement through Architecture Change in Artificial Neural Networks.
ISICA 2008: 248-257 |
| 2007 |
|---|
| 7 | EE | Pedro Ferreira,
Pedro Ribeiro,
Ana Antunes,
Fernando Morgado Dias:
A high bit resolution FPGA implementation of a FNN with a new algorithm for the activation function.
Neurocomputing 71(1-3): 71-77 (2007) |
| 2006 |
|---|
| 6 | EE | Ana Antunes,
Fernando Morgado Dias,
José Vieira,
Alexandre Mota:
Delay Compensator: an Approach to Reduce the Variable Sampling to Actuation Delay Effect in Distributed Real-time Control Systems.
ETFA 2006: 531-536 |
| 5 | EE | Fernando Morgado Dias,
Ana Antunes,
José Vieira,
Alexandre Manuel Mota:
On-Line Learning of a Time Variant System.
IEA/AIE 2006: 908-916 |
| 2005 |
|---|
| 4 | EE | Jose Antonio Vieira,
Fernando Morgado Dias,
Alexandre Manuel Mota:
Hybrid Neuro-Fuzzy Network-Priori Knowledge Model in Temperature Control of a Gas Water Heater System.
HIS 2005: 116-124 |
| 3 | EE | Fernando Morgado Dias,
Ana Antunes,
José Vieira,
Alexandre Manuel Mota:
Using the Levenberg-Marquardt for On-line Training of a Variant System.
ICANN (2) 2005: 359-364 |
| 2 | EE | Fernando Morgado Dias,
Ana Antunes,
José Vieira,
Alexandre Manuel Mota:
On-line Training of Neural Networks: A Sliding Window Approach for the Levenberg-Marquardt Algorithm.
IWINAC (2) 2005: 577-585 |
| 2004 |
|---|
| 1 | EE | Pedro Ferreira,
Pedro Ribeiro,
Ana Antunes,
Fernando Morgado Dias:
Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA.
FPL 2004: 1084-1086 |
