2008 |
29 | EE | Petru Bogdan Bacinschi,
Tudor Murgan,
Klaus Koch,
Manfred Glesner:
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.
DATE 2008: 698-703 |
28 | EE | Sujan Pandey,
Rolf Drechsler,
Tudor Murgan,
Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs.
ISCAS 2008: 2989-2992 |
27 | EE | Alberto García Ortiz,
Leandro Soares Indrusiak,
Tudor Murgan,
Manfred Glesner:
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.
PATMOS 2008: 219-228 |
26 | EE | Manfred Glesner,
Tudor Murgan,
Thomas Hollstein:
Hardware Based Rapid Prototyping.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
2007 |
25 | EE | Tudor Murgan,
Petru Bogdan Bacinschi,
Sujan Pandey,
Alberto García Ortiz,
Manfred Glesner:
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.
PATMOS 2007: 242-254 |
24 | | Heiko Hinkelmann,
Tudor Murgan,
G. Liu,
Peter Zipf,
Manfred Glesner:
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.
ReCoSoC 2007: 185-191 |
23 | | Tudor Murgan,
Andre Guntoro,
Heiko Hinkelmann,
Petru Bogdan Bacinschi,
Manfred Glesner:
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.
ReCoSoC 2007: 7-14 |
2006 |
22 | EE | Oliver Soffke,
Peter Zipf,
Tudor Murgan,
Manfred Glesner:
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.
DATE 2006: 632-637 |
21 | EE | Tudor Murgan,
Massoud Momeni,
Alberto García Ortiz,
Manfred Glesner:
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.
ICCAD 2006: 323-328 |
20 | EE | Tudor Murgan,
Petru Bogdan Bacinschi,
Alberto García Ortiz,
Manfred Glesner:
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.
PATMOS 2006: 169-180 |
19 | EE | Sujan Pandey,
Tudor Murgan,
Manfred Glesner:
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.
VLSI-SoC 2006: 296-301 |
18 | EE | Tudor Murgan,
O. Mitrea,
Sujan Pandey,
Petru Bogdan Bacinschi,
Manfred Glesner:
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
VLSI-SoC 2006: 302-307 |
2005 |
17 | EE | Alberto García Ortiz,
Tudor Murgan,
Mihail Petrov,
Manfred Glesner:
A linear model for high-level delay estimation in VDSM on-chip interconnects.
ISCAS (2) 2005: 1078-1081 |
16 | EE | A. Petrov,
Tudor Murgan,
Peter Zipf,
Manfred Glesner:
Functional modeling techniques for a wireless LAN OFDM transceiver.
ISCAS (4) 2005: 3970-3973 |
15 | | Tudor Murgan,
Abdulfattah Mohammad Obeid,
Andre Guntoro,
Peter Zipf,
Manfred Glesner,
Ulrich Heinkel:
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks.
ReCoSoC 2005: 151-156 |
14 | EE | Manfred Glesner,
Heiko Hinkelmann,
Thomas Hollstein,
Leandro Soares Indrusiak,
Tudor Murgan,
Abdulfattah Mohammad Obeid,
Mihail Petrov,
Thilo Pionteck,
Peter Zipf:
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.
SAMOS 2005: 12-21 |
2004 |
13 | EE | Manfred Glesner,
Thomas Hollstein,
Leandro Soares Indrusiak,
Peter Zipf,
Thilo Pionteck,
Mihail Petrov,
Heiko Zimmer,
Tudor Murgan:
Reconfigurable platforms for ubiquitous computing.
Conf. Computing Frontiers 2004: 377-389 |
12 | EE | Tudor Murgan,
Mihail Petrov,
Mateusz Majer,
Peter Zipf,
Manfred Glesner,
Ulrich Heinkel,
Jörg Pleickhardt,
Bernd Bleisteiner:
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing.
Conf. Computing Frontiers 2004: 404-418 |
11 | EE | Mihail Petrov,
Tudor Murgan,
F. May,
Martin Vorbach,
Peter Zipf,
Manfred Glesner:
The XPP Architecture and Its Co-simulation Within the Simulink Environment.
FPL 2004: 761-770 |
10 | | Mihail Petrov,
Tudor Murgan,
Abdulfattah Mohammad Obeid,
Cristian Chitu,
Peter Zipf,
Jörg Brakensiek,
Manfred Glesner:
Dynamic power optimization of the trace-back process for the Viterbi algorithm.
ISCAS (2) 2004: 721-724 |
9 | EE | Tudor Murgan,
Alberto García Ortiz,
Clemens Schlachta,
Heiko Zimmer,
Mihail Petrov,
Manfred Glesner:
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.
PATMOS 2004: 819-828 |
8 | EE | Alberto García Ortiz,
Tudor Murgan,
Manfred Glesner:
Moment-Based Estimation of Switching Activity for Correlated Distributions.
PATMOS 2004: 859-868 |
7 | EE | Tudor Murgan,
Clemens Schlachta,
Mihail Petrov,
Leandro Soares Indrusiak,
Alberto García Ortiz,
Manfred Glesner,
Ricardo A. L. Reis:
Accurate capture of timing parameters in inductively-coupled on-chip interconnects.
SBCCI 2004: 117-122 |
2003 |
6 | EE | Tudor Murgan,
Mihail Petrov,
Alberto García Ortiz,
Ralf Ludewig,
Peter Zipf,
Thomas Hollstein,
Manfred Glesner,
Bernard Ölkrug,
Jörg Brakensiek:
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures.
FPL 2003: 1111-1114 |
5 | EE | Alberto García Ortiz,
Lukusa D. Kabulepa,
Tudor Murgan,
Manfred Glesner:
Moment-Based Power Estimation in Very Deep Submicron Technologies.
ICCAD 2003: 107-112 |
4 | EE | Ralf Ludewig,
Alberto García Ortiz,
Tudor Murgan,
Juan Jesus,
Ocampo Hidalgo,
Manfred Glesner:
Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems.
IEEE International Workshop on Rapid System Prototyping 2003: 172-178 |
3 | EE | Alberto García Ortiz,
Tudor Murgan,
Manfred Glesner:
Transition Activity Estimation for General Correlated Data Distributions.
VLSI Design 2003: 440-445 |
2 | | Mihail Petrov,
Abdulfattah Mohammad Obeid,
Tudor Murgan,
Peter Zipf,
Jörg Brakensiek,
Bernard Ölkrug,
Manfred Glesner:
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders.
VLSI-SOC 2003: 167- |
2002 |
1 | EE | Ralf Ludewig,
Alberto García Ortiz,
Tudor Murgan,
Manfred Glesner:
Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System.
IEEE International Workshop on Rapid System Prototyping 2002: 138- |