dblp.uni-trier.dewww.uni-trier.de

Uwe Meyer-Bäse

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2007
18EEEncarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz: Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. FPL 2007: 183-188
17EEEncarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz: IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. IEEE Trans. VLSI Syst. 15(5): 578-591 (2007)
2006
16EEUwe Meyer-Bäse, Jiajia Chen, Chip-Hong Chang, Andrew G. Dempster: A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. APCCAS 2006: 1555-1558
15EEEncarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse: IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL 2006: 1-6
2005
14 Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz: Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. FPL 2005: 531-534
13EEJavier Ramírez, Uwe Meyer-Bäse, Antonio García: Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology. Journal of Circuits, Systems, and Computers 14(1): 165-177 (2005)
2004
12EEUwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García: Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. FPL 2004: 384-393
2003
11EEJavier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz: Design and Implementation of RNS-Based Adaptive Filters. FPL 2003: 1135-1138
10EEUwe Meyer-Bäse, Thanos Stouraitis: New power-of-2 RNS scaling scheme for cell-based IC design. IEEE Trans. VLSI Syst. 11(2): 280-283 (2003)
9EEJavier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz: Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. VLSI Signal Processing 33(1-2): 171-190 (2003)
8EEJavier Ramírez, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García, Antonio Lloris-Ruíz: Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. VLSI Signal Processing 34(3): 227-237 (2003)
2002
7EEUwe Meyer-Bäse, Javier Ramírez, Antonio García: Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. FPL 2002: 897-904
2001
6EEUwe Meyer-Bäse, Antonio García, Fred J. Taylor: Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. VLSI Signal Processing 28(1-2): 115-128 (2001)
1999
5EEAntonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor: RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. ISCAS (1) 1999: 486-489
1998
4EEUwe Meyer-Bäse, Anke Meyer-Bäse, J. D. Mellott, Fred J. Taylor: A Fast Modified CORDIC - Implementation of Radial Basis Neural Networks. VLSI Signal Processing 20(3): 211-218 (1998)
1996
3 Uwe Meyer-Bäse: Coherent Demodulation with FPGAs. FPL 1996: 166-175
2 Uwe Meyer-Bäse: Convolutional Error Decoding with FPGAs. FPL 1996: 376-380
1994
1 Uwe Meyer-Bäse, Anke Meyer-Bäse, W. Hilberg: COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA. FPL 1994: 397-408

Coauthor Index

1Encarnación Castillo [14] [15] [17] [18]
2Chip-Hong Chang [16]
3Jiajia Chen [16]
4Andrew G. Dempster [16]
5Antonio García [5] [6] [7] [8] [9] [11] [12] [13] [14] [15] [17] [18]
6W. Hilberg [1]
7Antonio Lloris-Ruíz [5] [8] [9] [11] [14] [15] [17] [18]
8J. D. Mellott [4]
9Anke Meyer-Bäse [1] [4]
10Luis Parrilla [15] [17] [18]
11Javier Ramírez [7] [8] [9] [11] [12] [13] [14]
12Suhasini Rao [12]
13Thanos Stouraitis [10]
14Fred J. Taylor [4] [5] [6] [8] [9]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)