2007 |
10 | EE | Encarnación Castillo,
Luis Parrilla,
Antonio García,
Uwe Meyer-Bäse,
Antonio Lloris-Ruíz:
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
FPL 2007: 183-188 |
9 | EE | Encarnación Castillo,
Uwe Meyer-Bäse,
Antonio García,
Luis Parrilla,
Antonio Lloris-Ruíz:
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores.
IEEE Trans. VLSI Syst. 15(5): 578-591 (2007) |
2006 |
8 | EE | Encarnación Castillo,
Luis Parrilla,
Antonio García,
Antonio Lloris-Ruíz,
Uwe Meyer-Bäse:
IPP Watermarking Technique for IP Core Protection on FPL Devices.
FPL 2006: 1-6 |
2005 |
7 | EE | Daniel González,
Luis Parrilla,
Antonio García,
Encarnación Castillo,
Antonio Lloris-Ruíz:
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers.
PATMOS 2005: 657-665 |
2004 |
6 | EE | Luis Parrilla,
Encarnación Castillo,
Antonio García,
Antonio Lloris-Ruíz:
Intellectual Property Protection for RNS Circuits on FPGAs.
FPL 2004: 1139-1141 |
2002 |
5 | EE | Daniel González,
Antonio García,
Graham A. Jullien,
Javier Ramírez,
Luis Parrilla,
Antonio Lloris-Ruíz:
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems.
PATMOS 2002: 188-197 |
2000 |
4 | EE | Javier Ramírez,
Antonio García,
Pedro G. Fernández,
Luis Parrilla,
Antonio Lloris-Ruíz:
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.
FPL 2000: 342-351 |
1999 |
3 | | Julio Ortega,
Luis Parrilla,
José Luis Bernier,
Consolación Gil,
Begoña Pino,
Mancia Anguita:
Adaptive Cooperation Between Processors in a Parallel Boltzmann Machine.
IWANN (2) 1999: 208-218 |
2 | EE | Luis Parrilla,
Julio Ortega,
Antonio Lloris-Ruíz:
Using PVM for Distributed Logic Minimization in a Network of Computers.
PVM/MPI 1999: 541-548 |
1997 |
1 | | Julio Ortega,
Luis Parrilla,
Alberto Prieto,
Antonio Lloris-Ruíz,
Carlos García Puntonet:
Modified Boltzmann Machine for an Efficient Distributed Implementation.
IWANN 1997: 1221-1232 |