Michiaki Muraoka

2004
11	EE	Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada: Design methodology for SoC arthitectures based on reusable virtual cores. ASP-DAC 2004: 256-262
2003
10	EE	Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara: A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium 2003: 130-135
9	EE	Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara: A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium 2003: 412-417
2002
8	EE	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka: A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium 2002: 305-310
7	EE	Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium 2002: 55-60
6	EE	Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS 2002: 328-335
1997
5	EE	Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu: A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium 1997: 306-
1996
4	EE	Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka: A Design for testability Method Using RTL Partitioning. Asian Test Symposium 1996: 88-93
1995
3	EE	Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka: Design for testability using register-transfer level partial scan selection. ASP-DAC 1995
1993
2	EE	Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin: A State Traversal Algorithm Using a State Covariance Matrix. DAC 1993: 97-101
1985
1	EE	Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa: ACTAS: an accurate timing analysis system for VLSI. DAC 1985: 152-158

Coauthor Index

1	Hiroshi Date	[6] [7] [8] [9] [10]
2	Hideo Fujiwara	[9] [10]
3	Hideyuki Hamada	[11]
4	Kazuyuki Hirakawa	[1]
5	Toshihiro Hiraoka	[5]
6	Toshinori Hosokawa	[2] [3] [4] [5] [6] [7] [8] [9] [10]
7	Hirokazu Iida	[1]
8	Kenichi Kawaguchi	[4]
9	Kazuhiro Kayashima	[2]
10	Hideyuki Kikuchihara	[1]
11	Shigeo Kuninobu	[5]
12	Hidetsugu Maekawa	[2]
13	Michihiro Matsumoto	[3]
14	Masahide Miyazaki	[9] [10]
15	Rafael K. Morizawa	[11]
16	Akira Motohara	[2] [3]
17	Michio Murakami	[1]
18	Hiroaki Nishi	[11]
19	Mitsuyasu Ohta	[3] [4] [5]
20	Yasuharu Shimeki	[2]
21	Seichi Shin	[2]
22	Yuji Takai	[3]
23	Sadami Takeoka	[3]
24	Hideaki Yokota	[11]

Colors in the list of coauthors