| 2005 |
|---|
| 4 | EE | Pedram A. Riahi,
Zainalabedin Navabi,
Fabrizio Lombardi:
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.
DFT 2005: 389-397 |
| 2003 |
|---|
| 3 | EE | Pedram A. Riahi,
Zainalabedin Navabi,
Fabrizio Lombardi:
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.
Asian Test Symposium 2003: 274-277 |
| 2 | EE | Shervin Sharifi,
Mohammad Hosseinabady,
Pedram A. Riahi,
Zainalabedin Navabi:
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
DFT 2003: 352-360 |
| 1 | | Pedram A. Riahi,
Zainalabedin Navabi,
Fabrizio Lombardi:
Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.
Embedded Systems and Applications 2003: 139-143 |
