Pan Zhongliang

2006
4	EE	Pan Zhongliang, Chen Ling, Liu Shouqiang, Guangzhao Zhang: Neural Network Approach for Multiple Fault Test of Digital Circuit. ISDA (3) 2006: 24-29
2004
3	EE	Pan Zhongliang: Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit. VLSI Design 2004: 499-
2003
2	EE	Pan Zhongliang: Fault Detection for Testable Realizations of Multiple-Valued Logic Functions. Asian Test Symposium 2003: 242-249
1	EE	Pan Zhongliang: Bridging Fault Detections for Testable Realizations of Logic Functions. VLSI Design 2003: 423-

Coauthor Index

1	Chen Ling	[4]
2	Liu Shouqiang	[4]
3	Guangzhao Zhang	[4]