2008 |
13 | EE | Ehsan Atoofian,
Amirali Baniasadi,
Yvonne Coady:
Adaptive Read Validation in Time-Based Software Transactional Memory.
Euro-Par Workshops 2008: 152-162 |
12 | EE | Ehsan Atoofian,
Amirali Baniasadi:
Exploiting program cyclic behavior to reduce memory latency in embedded processors.
SAC 2008: 1482-1486 |
11 | EE | Ehsan Atoofian,
Amirali Baniasadi:
Using supplier locality in power-aware interconnects and caches in chip multiprocessors.
Journal of Systems Architecture - Embedded Systems Design 54(5): 507-518 (2008) |
2007 |
10 | EE | Kaveh Aasaraai,
Amirali Baniasadi,
Ehsan Atoofian:
Computational and storage power optimizations for the O-GEHL branch predictor.
Conf. Computing Frontiers 2007: 105-112 |
9 | EE | Ehsan Atoofian,
Amirali Baniasadi,
Kaveh Aasaraai:
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols.
Conf. Computing Frontiers 2007: 259-266 |
8 | EE | Ehsan Atoofian,
Amirali Baniasadi:
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors.
IPDPS 2007: 1-8 |
7 | EE | Ehsan Atoofian,
Amirali Baniasadi,
Kaveh Aasaraai:
Exploiting Speculation Cost Prediction in Power-Aware Applications.
J. Low Power Electronics 3(1): 43-53 (2007) |
6 | EE | Ehsan Atoofian,
Amirali Baniasadi:
Speculative trivialization point advancing in high-performance processors.
Journal of Systems Architecture 53(9): 587-601 (2007) |
2006 |
5 | EE | Ehsan Atoofian,
Zainalabedin Navabi:
A Test Approach for Look-Up Table Based FPGAs.
J. Comput. Sci. Technol. 21(1): 141-146 (2006) |
2005 |
4 | EE | Ehsan Atoofian,
Amirali Baniasadi:
Improving Energy-Efficiency by Bypassing Trivial Computations.
IPDPS 2005 |
3 | EE | Mohammad Alisafaee,
Safar Hatami,
Ehsan Atoofian,
Zainalabedin Navabi,
Ali Afzali-Kusha:
A low-power scan-path architecture.
ISCAS (5) 2005: 5278-5281 |
2003 |
2 | EE | Ehsan Atoofian,
Zainalabedin Navabi:
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.
Asian Test Symposium 2003: 84-89 |
1 | | Ehsan Atoofian,
Zainalabedin Navabi:
A Low Power BIST Architecture for FPGA Look-Up Table Testing.
VLSI-SOC 2003: 394-397 |