2009 |
29 | EE | Koji Yamazaki,
Toshiyuki Tsutsumi,
Hiroshi Takahashi,
Yoshinobu Higami,
Takashi Aikyo,
Yuzo Takamatsu,
Hiroyuki Yotsuyanagi,
Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis.
VLSI Design 2009: 85-90 |
28 | EE | Hiroyuki Yotsuyanagi,
Masaki Hashizume,
Toshiyuki Tsutsumi,
Koji Yamazaki,
Takashi Aikyo,
Yoshinobu Higami,
Hiroshi Takahashi,
Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
VLSI Design 2009: 91-96 |
2007 |
27 | EE | Hiroshi Takahashi,
Yoshinobu Higami,
Toru Kikkawa,
Takashi Aikyo,
Yuzo Takamatsu,
Hiroyuki Yotsuyanagi,
Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
DFT 2007: 243-251 |
2006 |
26 | EE | Masaki Hashizume,
Tomomi Nishida,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada,
Yukiya Miura:
Current Testable Design of Resistor String DACs.
DELTA 2006: 197-200 |
2005 |
25 | EE | Masaki Hashizume,
Masahiro Ichimiya,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
Electric field for detecting open leads in CMOS logic circuits by supply current testing.
ISCAS (3) 2005: 2995-2998 |
24 | EE | Hiroyuki Yotsuyanagi,
Toshimasa Kuchii,
Shigeki Nishikawa,
Masaki Hashizume,
Kozo Kinoshita:
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.
J. Electronic Testing 21(6): 613-620 (2005) |
2004 |
23 | EE | Masaki Hashizume,
Daisuke Yoneda,
Hiroyuki Yotsuyanagi,
Tetsuo Tada,
Takeshi Koyama,
Ikuro Morita,
Takeomi Tamesada:
I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment.
Asian Test Symposium 2004: 112-117 |
22 | EE | Masaki Hashizume,
Tetsuo Akita,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
CMOS Open Fault Detection by Appearance Time of Switching Supply Current.
DELTA 2004: 183-188 |
21 | EE | Isao Tsukimoto,
Masaki Hashizume,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
Practical Fault Coverage of Supply Current Tests for Bipolar ICs.
DELTA 2004: 189-194 |
20 | EE | Hiroyuki Yotsuyanagi,
Toshimasa Kuchii,
Shigeki Nishikawa,
Masaki Hashizume,
Kozo Kinoshita:
On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.
DELTA 2004: 269-274 |
19 | EE | Daisuke Ezaki,
Masaki Hashizume,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
A Power Supply Circuit Recycling Charge in Adiabatic Dynamic CMOS Logic Circuits.
DELTA 2004: 306-311 |
18 | EE | Masahiro Ichimiya,
Masaki Hashizume,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
A test circuit for pin shorts generating oscillation in CMOS logic circuits.
Systems and Computers in Japan 35(13): 10-20 (2004) |
2003 |
17 | EE | Masaki Hashizume,
Teppei Takeda,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada,
Yukiya Miura,
Kozo Kinoshita:
A BIST Circuit for IDDQ Tests.
Asian Test Symposium 2003: 390-395 |
16 | EE | Hiroyuki Yotsuyanagi,
Toshimasa Kuchii,
Shigeki Nishikawa,
Masaki Hashizume,
Kozo Kinoshita:
Reducing Scan Shifts Using Folding Scan Trees.
Asian Test Symposium 2003: 6-11 |
2002 |
15 | EE | Hiroyuki Yotsuyanagi,
Masaki Hashizume,
Takeomi Tamesada:
Test Time Reduction for I DDQ Testing by Arranging Test Vectors.
Asian Test Symposium 2002: 423-428 |
14 | EE | Hiroyuki Yotsuyanagi,
Masaki Hashizume,
Taisuke Iwakiri,
Masahiro Ichimiya,
Takeomi Tamesada:
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field.
DELTA 2002: 387-391 |
13 | EE | Masaki Hashizume,
Masashi Sato,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
Power Supply Circuit for High Speed Operation of Adiabatic Dynamic CMOS Logic Circuits.
DELTA 2002: 459-461 |
2001 |
12 | EE | Teppei Takeda,
Masaki Hashizume,
Masahiro Ichimiya,
Hiroyuki Yotsuyanagi,
Yukiya Miura,
Kozo Kinoshita:
IDDQ Sensing Technique for High Speed IDDQ Testing.
Asian Test Symposium 2001: 111-116 |
11 | EE | Masaki Hashizume,
Masahiro Ichimiya,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application.
Asian Test Symposium 2001: 117-122 |
10 | EE | Hiroyuki Yotsuyanagi,
Shinsuke Hata,
Masaki Hashizume,
Takeomi Tamesada:
Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States.
Asian Test Symposium 2001: 23- |
9 | EE | Masaki Hashizume,
Masahiro Ichimiya,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
CMOS open defect detection by supply current test.
DATE 2001: 509 |
8 | EE | Hiroyuki Yotsuyanagi,
Masaki Hashizume,
Taisuke Iwakiri,
Masahiro Ichimiya,
Takeomi Tamesada:
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field.
DFT 2001: 287- |
2000 |
7 | EE | Masaki Hashizume,
Hiroyuki Yotsuyanagi,
Masahiro Ichimiya,
Takeomi Tamesada,
Masashi Takeda:
High speed IDDQ test and its testability for process variation.
Asian Test Symposium 2000: 344-349 |
6 | EE | Masaki Hashizume,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada,
Masashi Takeda:
Testability Analysis of IDDQ Testing with Large Threshold Value.
DFT 2000: 367-375 |
1999 |
5 | EE | Masaki Hashizume,
Hiroyuki Yotsuyanagi,
Takeomi Tamesada:
Identification of Feedback Bridging Faults with Oscillation.
Asian Test Symposium 1999: 25- |
1998 |
4 | EE | Hiroyuki Yotsuyanagi,
Kozo Kinoshita:
Undetectable Fault Removal of Sequential Circuits Based on Unreachable States.
VTS 1998: 176-183 |
1997 |
3 | EE | Hiroyuki Yotsuyanagi,
Seiji Kajihara,
Kozo Kinoshita:
Synthesis of Sequential Circuits by Redundancy Removal and Retiming.
J. Electronic Testing 11(1): 81-92 (1997) |
1995 |
2 | | Hiroyuki Yotsuyanagi,
Seiji Kajihara,
Kozo Kinoshita:
Synthesis for Testability by Sequential Redundancy Removal Using Retiming.
FTCS 1995: 33-40 |
1 | EE | Hiroyuki Yotsuyanagi,
Seiji Kajihara,
Kozo Kinoshita:
Resynthesis for sequential circuits designed with a specified initial state.
VTS 1995: 152-157 |