| 2006 |
|---|
| 7 | EE | Görschwin Fey,
Junhao Shi,
Rolf Drechsler:
Efficiency of Multi-Valued Encoding in SAT-based ATPG.
ISMVL 2006: 25 |
| 2005 |
|---|
| 6 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler:
Bridging fault testability of BDD circuits.
ASP-DAC 2005: 188-191 |
| 5 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
ISVLSI 2005: 212-217 |
| 2004 |
|---|
| 4 | EE | Görschwin Fey,
Junhao Shi,
Rolf Drechsler:
BDD Circuit Optimization for Path Delay Fault Testability.
DSD 2004: 168-172 |
| 3 | EE | Rolf Drechsler,
Junhao Shi,
Görschwin Fey:
Synthesis of fully testable circuits from BDDs.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004) |
| 2003 |
|---|
| 2 | EE | Rolf Drechsler,
Junhao Shi,
Görschwin Fey:
MuTaTe: an efficient design for testability technique for multiplexor based circuits.
ACM Great Lakes Symposium on VLSI 2003: 80-83 |
| 1 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler:
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
Asian Test Symposium 2003: 290-293 |
