2009 |
38 | EE | Youssef Benabboud,
Alberto Bosio,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Laroussi Bouzaida,
Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip.
ISQED 2009: 253-259 |
2008 |
37 | EE | A. Ney,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian,
V. Gouin:
A Design-for-Diagnosis Technique for SRAM Write Drivers.
DATE 2008: 1480-1485 |
36 | EE | Alexandre Rousset,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Improving Diagnosis Resolution without Physical Information.
DELTA 2008: 210-215 |
35 | EE | Julien Vial,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Using TMR Architectures for Yield Improvement.
DFT 2008: 7-15 |
34 | EE | A. Ney,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian,
V. Gouin:
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.
VTS 2008: 89-94 |
33 | EE | Nabil Badereddine,
Zhanglei Wang,
Patrick Girard,
Krishnendu Chakrabarty,
Arnaud Virazel,
Serge Pravossoudovitch,
Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electronic Testing 24(4): 353-364 (2008) |
2007 |
32 | EE | A. Ney,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Slow write driver faults in 65nm SRAM technology: analysis and March test solution.
DATE 2007: 528-533 |
31 | | Alexandre Rousset,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis.
DDECS 2007: 239-242 |
30 | EE | Alexandre Rousset,
Alberto Bosio,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
DERRIC: A Tool for Unified Logic Diagnosis.
European Test Symposium 2007: 13-20 |
29 | EE | O. Ginez,
Jean Michel Daga,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.
European Test Symposium 2007: 77-84 |
28 | EE | A. Ney,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.
European Test Symposium 2007: 97-104 |
27 | EE | A. Ney,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.
VTS 2007: 361-368 |
26 | EE | O. Ginez,
Jean Michel Daga,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.
VTS 2007: 47-52 |
25 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.
J. Electronic Testing 23(5): 435-444 (2007) |
2006 |
24 | | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.
DDECS 2006: 256-261 |
23 | EE | Nabil Badereddine,
Patrick Girard,
Serge Pravossoudovitch,
Christian Landrault,
Arnaud Virazel,
Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
VLSI-SoC 2006: 403-408 |
22 | EE | O. Ginez,
Jean Michel Daga,
Marylene Combe,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories.
VTS 2006: 108-113 |
21 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electronic Testing 22(1): 89-99 (2006) |
20 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri,
Magali Bastian Hage-Hassan:
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.
J. Electronic Testing 22(3): 287-296 (2006) |
2005 |
19 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.
DAC 2005: 857-862 |
18 | EE | Nabil Badereddine,
Patrick Girard,
Arnaud Virazel,
Serge Pravossoudovitch,
Christian Landrault:
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.
PATMOS 2005: 540-549 |
17 | EE | Nabil Badereddine,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Christian Landrault:
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.
VLSI-SoC 2005: 267-281 |
16 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.
VTS 2005: 183-188 |
15 | EE | Simone Borri,
Magali Bastian Hage-Hassan,
Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel:
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.
J. Electronic Testing 21(2): 169-179 (2005) |
14 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri,
Magali Bastian Hage-Hassan:
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.
J. Electronic Testing 21(5): 551-561 (2005) |
2004 |
13 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri,
Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.
Asian Test Symposium 2004: 266-271 |
12 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DATE 2004: 62-67 |
11 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DELTA 2004: 287-294 |
10 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri:
March iC-: An Improved Version of March C- for ADOFs Detection.
VTS 2004: 129-138 |
2003 |
9 | EE | Luigi Dilillo,
Patrick Girard,
Serge Pravossoudovitch,
Arnaud Virazel,
Simone Borri:
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.
Asian Test Symposium 2003: 250-255 |
2002 |
8 | EE | René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
On Using Efficient Test Sequences for BIST.
VTS 2002: 145-152 |
7 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment.
IEEE Design & Test of Computers 19(5): 44-52 (2002) |
6 | EE | René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Hardware Generation of Random Single Input Change Test Sequences.
J. Electronic Testing 18(2): 145-157 (2002) |
2001 |
5 | | René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST.
VLSI-SOC 2001: 413-424 |
4 | EE | Arnaud Virazel,
René David,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.
J. Electronic Testing 17(3-4): 233-241 (2001) |
2000 |
3 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.
IOLTW 2000: 121-126 |
1999 |
2 | EE | Patrick Girard,
Christian Landrault,
V. Moreda,
Serge Pravossoudovitch,
Arnaud Virazel:
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.
J. Electronic Testing 14(1-2): 95-102 (1999) |
1998 |
1 | EE | Patrick Girard,
Christian Landrault,
V. Moreda,
Serge Pravossoudovitch,
Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment.
Asian Test Symposium 1998: 435-439 |