2005 | ||
---|---|---|
5 | EE | Marong Phadoongsidhi, Kewal K. Saluja: SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. VLSI Design 2005: 820-823 |
2004 | ||
4 | EE | Marong Phadoongsidhi, Kewal K. Saluja: Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. VLSI Design 2004: 437-442 |
2003 | ||
3 | EE | Marong Phadoongsidhi, Kewal K. Saluja: Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. ICCD 2003: 42-47 |
2002 | ||
2 | EE | Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja: A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2002: 182- |
2001 | ||
1 | EE | Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu: Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63- |
1 | Yoshinobu Higami | [1] |
2 | Kim T. Le | [2] |
3 | Kewal K. Saluja | [1] [2] [3] [4] [5] |
4 | Hiroshi Takahashi | [1] |
5 | Yuzo Takamatsu | [1] |