2002 |
10 | EE | Kazuya Shimizu,
Noriyoshi Itazaki,
Kozo Kinoshita:
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits.
Asian Test Symposium 2002: 176-181 |
9 | EE | Kazuya Shimizu,
Masaya Takamura,
Takanori Shirai,
Noriyoshi Itazaki,
Kozo Kinoshita:
Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.
DELTA 2002: 92-98 |
8 | EE | Kazuya Shimizu,
Noriyoshi Itazaki,
Kozo Kinoshita:
Built-in Self-Test for crosstalk faults in a digital VLSI.
Systems and Computers in Japan 33(13): 35-47 (2002) |
2001 |
7 | EE | Kazuya Shimizu,
Noriyoshi Itazaki,
Kozo Kinoshita:
Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits.
Asian Test Symposium 2001: 469 |
1998 |
6 | EE | Noriyoshi Itazaki,
Fumiro Matsuki,
Yasuyuki Matsumoto,
Kozo Kinoshita:
Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.
Asian Test Symposium 1998: 272-277 |
1997 |
5 | EE | Noriyoshi Itazaki,
Yasutaka Idomoto,
Kozo Kinoshita:
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits.
Asian Test Symposium 1997: 22- |
1996 |
4 | | Noriyoshi Itazaki,
Yasutaka Idomoto,
Kozo Kinoshita:
A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits.
FTCS 1996: 38-43 |
1994 |
3 | EE | Antonio Rubio,
Noriyoshi Itazaki,
Xiaole Xu,
Kozo Kinoshita:
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 387-395 (1994) |
1989 |
2 | EE | Noriyoshi Itazaki,
Kozo Kinoshita:
Test pattern generation for circuits with tri-state modules by Z-algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1327-1334 (1989) |
1986 |
1 | | Noriyoshi Itazaki,
Kozo Kinoshita:
Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm.
ITC 1986: 105-112 |