| 2001 |
|---|
| 8 | EE | Parag K. Lala,
Alvernon Walker:
A Unified Scheme for Designing Testable State Machines.
Asian Test Symposium 2001: 273-278 |
| 7 | EE | Alvernon Walker:
A Step Response Based Mixed-Signal BIST Approach .
DFT 2001: 329-337 |
| 6 | EE | Parag K. Lala,
Alvernon Walker:
On-Line Error Detectable Carry-Free Adder Design.
DFT 2001: 66-71 |
| 2000 |
|---|
| 5 | EE | Parag K. Lala,
Alvernon Walker:
An On-Line Reconfigurable FPGA Architecture.
DFT 2000: 275- |
| 4 | EE | Alvernon Walker,
Parag K. Lala:
A Transition Based BIST Approach for Passive Analog Circuits.
ISQED 2000: 347-354 |
| 1999 |
|---|
| 3 | EE | Parag K. Lala,
Anup Singh,
Alvernon Walker:
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.
DFT 1999: 238-246 |
| 1997 |
|---|
| 2 | EE | Alvernon Walker,
Algernon P. Henry,
Parag K. Lala:
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.
DFT 1997: 272-280 |
| 1992 |
|---|
| 1 | EE | Alvernon Walker,
Winser E. Alexander,
Parag K. Lala:
Fault Diagnosis in Analog Circuits Using Element Modulation.
IEEE Design & Test of Computers 9(1): 19-29 (1992) |
