| 2007 |
|---|
| 8 | EE | Hao San,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Akira Hayakawa,
Haruo Kobayashi,
Masao Hotta:
A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.
ASP-DAC 2007: 96-97 |
| 7 | EE | Hao San,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Akira Hayakawa,
Haruo Kobayashi,
Tatsuji Matsuura,
Kouichi Yahagi,
Junya Kudoh,
Hideo Nakane,
Masao Hotta,
Toshiro Tsukada,
Koichiro Mashiko,
Atsushi Wada:
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Transactions 90-C(6): 1181-1188 (2007) |
| 2006 |
|---|
| 6 | EE | Hao San,
Akira Hayakawa,
Yoshitaka Jingu,
Hiroki Wada,
Hiroyuki Hagiwara,
Kazuyuki Kobayashi,
Haruo Kobayashi,
Tatsuji Matsuura,
Kouichi Yahagi,
Junya Kudoh,
Hideo Nakane,
Masao Hotta,
Toshiro Tsukada,
Koichiro Mashiko,
Atsushi Wada:
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Transactions 89-A(4): 908-915 (2006) |
| 2001 |
|---|
| 5 | EE | Satoshi Ohtake,
Shintaro Nagai,
Hiroki Wada,
Hideo Fujiwara:
A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability.
ASP-DAC 2001: 331-334 |
| 4 | EE | Ken-ichi Yamaguchi,
Hiroki Wada,
Toshimitsu Masuzawa,
Hideo Fujiwara:
BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths.
Asian Test Symposium 2001: 313-318 |
| 2000 |
|---|
| 3 | EE | Satoshi Ohtake,
Hiroki Wada,
Toshimitsu Masuzawa,
Hideo Fujiwara:
A non-scan DFT method at register-transfer level to achieve complete fault efficiency.
ASP-DAC 2000: 599-604 |
| 2 | EE | Toshimitsu Masuzawa,
Minoru Izutsu,
Hiroki Wada,
Hideo Fujiwara:
Single-control testability of RTL data paths for BIST.
Asian Test Symposium 2000: 210-215 |
| 1 | EE | Hiroki Wada,
Toshimitsu Masuzawa,
Kewal K. Saluja,
Hideo Fujiwara:
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency.
VLSI Design 2000: 300-305 |
