| |
| 2001 | ||
|---|---|---|
| 4 | EE | Toshinobu Ono, Akira Kozawa, Takashi Kimura, Yoshihiro Konno, Koji Saga: An Application of Partial Scan Techniques to a High-End System LSI Design. Asian Test Symposium 2001: 459 |
| 1997 | ||
| 3 | EE | Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida: Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. Asian Test Symposium 1997: 122-125 |
| 1994 | ||
| 2 | EE | Toshinobu Ono: Selecting partial scan flip-flops for circuit partitioning. ICCAD 1994: 646-650 |
| 1991 | ||
| 1 | Toshinobu Ono, Masaaki Yoshida: A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States. ITC 1991: 75-82 | |
| 1 | Hitoshi Hikima | [3] |
| 2 | Takashi Kimura | [4] |
| 3 | Yoshihiro Konno | [4] |
| 4 | Akira Kozawa | [4] |
| 5 | Yoshiyuki Nakamura | [3] |
| 6 | Koji Saga | [4] |
| 7 | Kazuo Wakui | [3] |
| 8 | Masaaki Yoshida | [1] [3] |