| 2008 |
|---|
| 4 | EE | Chia-Ming Chang,
Shih-Hsu Huang,
Yuan-Kai Ho,
Jia-Zong Lin,
Hsin-Po Wang,
Yu-Sheng Lu:
Type-matching clock tree for zero skew clock gating.
DAC 2008: 714-719 |
| 2001 |
|---|
| 3 | EE | Chih-Wea Wang,
Ruey-Shing Tzeng,
Chi-Feng Wu,
Chih-Tsun Huang,
Cheng-Wen Wu,
Shi-Yu Huang,
Shyh-Horng Lin,
Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
Asian Test Symposium 2001: 103- |
| 2 | EE | Xiaoqing Wen,
Hsin-Po Wang:
A Flexible Logic BIST Scheme and Its Application to SoC Designs.
Asian Test Symposium 2001: 463 |
| 2000 |
|---|
| 1 | EE | Hsin-Po Wang,
Jon Turino:
DFT and BIST techniques for the future.
Asian Test Symposium 2000: 6-7 |
