Pierluigi Civera

2003
12	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New techniques for efficiently assessing reliability of SOCs. Microelectronics Journal 34(1): 53-61 (2003)
2002
11	EE	Pierluigi Civera, Luca Macchiarulo, Massimo Violante: A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT 2002: 31-39
10	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electronic Testing 18(3): 261-271 (2002)
2001
9	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304-
8	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258
7	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502
6	EE	Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13
2000
5	EE	Crina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo: RTL Estimation of Steering Logic Power. PATMOS 2000: 36-46
1999
4		Luca Macchiarulo, Pierluigi Civera: Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. VLSI Design 1999: 218-
1998
3	EE	Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera: An Integrated HW and SW Fault Injection Environment for Real-Time Systems. DFT 1998: 117-
2	EE	Luca Macchiarulo, Pierluigi Civera: Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. ISMVL 1998: 58-
1987
1		Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni: An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA 1987: 117-126

Coauthor Index

1	Crina Anton	[5]
2	Alfredo Benso	[3]
3	Alessandro Bogliolo	[5]
4	Ionel Colonescu	[5]
5	Luca Macchiarulo	[2] [4] [6] [7] [8] [9] [10] [11] [12]
6	Enrico Macii	[5]
7	F. Maddaleno	[1]
8	Gianluca Piccinini	[1]
9	Massimo Poncino	[5]
10	Maurizio Rebaudengo	[3] [6] [7] [8] [9] [10] [12]
11	Matteo Sonza Reorda	[3] [6] [7] [8] [9] [10] [12]
12	Massimo Violante	[6] [7] [8] [9] [10] [11] [12]
13	Maurizio Zamboni	[1]

Colors in the list of coauthors