ITC 1988:
Washington,
D.C.,
USA
Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988.
IEEE Computer Society 1988 BibTeX
@proceedings{DBLP:conf/itc/1988,
title = {Proceedings International Test Conference 1988, Washington, D.C.,
USA, September 1988},
booktitle = {ITC},
publisher = {IEEE Computer Society},
year = {1988},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Plenary:
Keynote Address and Invited Speakers
Keynote Speaker
Invited Speakers
Session 2:
New Advances in Test Hardware
Session 3:
Board Test:
New Problems and Applications
Session 4:
Testing Microprocessors:
A Life Cycle's Work
Session 5:
Software and Hardware Approaches to Fault Simulation
Session 6:
Ultimate:
The Wave of the Future
- Teruo Tamama, Naoaki Narumi, Taiichi Otsuji, Masao Suzuki, Tsuneta Sudo:
Key Technologies for 500 MHz VLSI Test System "ULTIMATE".
108-113 BibTeX
- T. Adachi, M. Tanno, Tsuneta Sudo:
Software Environment for 500 MHz VLSI Test System "ULTIMATE".
114-119 BibTeX
- Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo:
Packaging Technologies for the 500 MHz VLSI Test System "ULTIMATE".
120-125 BibTeX
Session 7:
Boundary Scan and Test Bus
Session 8:
Test Features of Today's Microprocessors
Session 9:
Panel Session:
What ist the Path to Fast Fault Simulation?
Session 10:
Panel Session:
Componenent ATE Timing Accuracy Specifications:
Can We Standardize?
Session 11:
Panel Sesssion:
Testability Standards
Session 13:
Panel Session Test Education:
Linking Theory and Practice
Session 14:
High-Level Test Generation
Session 15:
Weighted Pseudorandom Pattern Genereation for BIST
Session 16:
RAM Design for Test
Session 17:
Quality,
Yield,
and the Cost of Test
Session 19:
Design and Evaluation of Signature Analysis Based BIST
Session 20:
SRAM Test Methods
Session 21:
Reliability Test Detection Strategies
Session 22:
Board Test Technology and Practice
Session 23:
BIST Control and Test Scheduling
Session 24:
CAE and Workstations I
Session 25:
Realistic Defects and Their Impact on Shipped Quality
Session 26:
Panel Session:
High Frequency DUT-Tester Interconnection Problems
Session 27:
Implementation and Analysis of BIST
Session 28:
CAE and Workstations II
Session 29:
Advances in Ffault Simulation and Fault Modeling
Session 30:
High-Speed Probing
Session 31:
Design for Testability I
Session 32:
Testing ASICs
Session 33:
Test Generation:
Techniques
Session 34:
Novel Test Techniques Using Optics
Session 35:
Design for Testability II
- M. M. Pradhan, E. J. O'Brien, S. L. Lam, James Beausang:
Circular BIST with Partial Scan.
719-729 BibTeX
- Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli:
An Incomplete Scan Design Approach to Test Generation for Sequential Machines.
730-734 BibTeX
- S. Bhawmick, M. S. Khaira, P. P. Mishra, A. Das, A. Dasgupta, P. Palchaudhury:
Threading of Multiple Scan Paths in a VLSI Circuit.
735-743 BibTeX
Session 36:
Mixed-Signal Testing
Session 37:
Test Generation:
Algorithms
Session 38:
Process Improvement:
Data in Action
Session 39:
Analog Design for Testability
Session 40:
Test Generation:
Delay Testing
Session 41:
Systems Test I
Session 42:
E-Beam Concepts
- M. Melgara, M. Battu, P. Garino, J. Dowe, Y. J. Vernay, M. Marzouki, F. Boland:
Automatic Location of IC Design Errors Using Beam System.
898-907 BibTeX
- Hironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum:
Electron Beam Tester Integrated into a VLSI Tester.
908-913 BibTeX
Session 43:
Concurrent BIST Techniques
Session 44:
VLSI Processor Test:
Techniques and Technology
Session 45:
Systems Test II
Poster Session
Copyright © Sat May 16 23:26:41 2009
by Michael Ley (ley@uni-trier.de)
