IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 9

Volume 9, Number 1, January 1990

• Chin-Long Wey, Tsin-Yuan Chang:
  An efficient output phase assignment for PLA minimization. 1-7
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• Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  Irredundant sequential machines via optimal logic synthesis. 8-18
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• Prathima Agrawal, William J. Dally:
  A hardware logic simulation system. 19-29
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• David M. Lewis:
  Device model approximation using 2^N trees. 30-38
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• Sanae Fukuda, Naoyuki Shigyo, Koichi Kato, Shin Nakamura:
  A ULSI 2-D capacitance simulator for complex structures based on actual processes. 39-47
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• Taoyun Wang, Joseph R. Mautz, Roger F. Harrington:
  The excess capacitance of a microstrip via in a dielectric substrate. 48-56
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• Adam D. Sherer, Bob S. Stanojevich, Robert J. Bowman:
  SMALS: a novel database for two-dimensional object location. 57-65
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• David Marple, Michiel Smulders, Henk Hegen:
  Tailor: a layout system based on trapezoidal corner stitching. 66-90
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• Youssef Saab, Vasant B. Rao:
  Fast effective heuristics for the graph bisectioning problem. 91-98
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• Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg:
  A first-order charge conserving MOS capacitance model. 99-108
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Volume 9, Number 2, February 1990

• Han Young Koh, Carlo H. Séquin, Paul R. Gray:
  OPASYN: a compiler for CMOS operational amplifiers. 113-125
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• Don Stark, Mark Horowitz:
  Techniques for calculating currents and voltages in VLSI power supply networks. 126-132
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• Genhong Ruan, Jiri Vlach, James A. Barby:
  Logic simulation with current-limited switches. 133-141
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• Gregory T. Brauns, R. J. Bishop, Michael Steer, John J. Paulos, Sasan H. Ardalan:
  Table-based modeling of delta-sigma modulators using ZSIM. 142-150
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• Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
  Hybrid routing. 151-157
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• Kurt Mehlhorn, Stefan Näher:
  A faster compaction algorithm with automatic jog insertion. 158-166
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• Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin:
  'Zone-refining' techniques for IC layout compaction. 167-179
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• Michael Kaufmann:
  A linear-time algorithm for routing in a convex grid. 180-184
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• Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong:
  New algorithms for the rectilinear Steiner tree problem. 185-193
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• Ronald F. Ayres:
  Completely automatic completion of VLSI designs. 194-202
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• Sunggu Lee, Kang G. Shin:
  Design for test using partial parallel scan. 203-211
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• Fadi Maamari, Janusz Rajski:
  A method of fault simulation based on stem regions. 212-220
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Volume 9, Number 3, March 1990

• Makiko Okumura, Tsutomu Sugawara, Hiroshi Tanimoto:
  An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations. 225-235
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• Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks:
  Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. 236-247
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• Wim De Pauw, Ludo Weyten:
  Multiple storage adaptive multi-trees. 248-252
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• Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf:
  Temperature measurement and equilibrium dynamics of simulated annealing placements. 253-259
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• John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya:
  Two-dimensional IC layout compaction based on topological design rule checking. 260-275
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• Razali Ismail, Gehan Amaratunga:
  Adaptive meshing schemes for simulating dopant diffusion. 276-289
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• W. Scott Stornetta, Bernardo A. Huberman, Tad Hogg:
  Scaling theory for fault stealing algorithms in large systolic arrays. 290-298
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• Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski:
  On computing the sizes of detected delay faults. 299-312
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• Srinivas Patil, Prithviraj Banerjee:
  A parallel branch and bound algorithm for test generation. 313-322
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• Wei-Kang Huang, Yinan N. Shen, Fabrizio Lombardi:
  New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement. 323-328
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• Sreejit Chakravarty, S. S. Ravi:
  Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. 329-331
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• Niraj K. Jha:
  Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. 332-336
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Volume 9, Number 4, April 1990

• Daniel Weise:
  Multilevel verification of MOS circuits. 341-351
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• Lawrence T. Pillage, Ronald A. Rohrer:
  Asymptotic waveform evaluation for timing analysis. 352-366
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• An-Chang Deng, Yan-Chyuan Shiau:
  Generic linear RC delay modeling for digital CMOS circuits. 367-376
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• San-Yuan Wu, Sartaj Sahni:
  Covering rectilinear polygons by rectangles. 377-388
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• Kurt Mehlhorn, Wolfgang Rülling:
  Compaction on the torus [VLSI layout]. 389-397
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• James P. Cohoon, Dana S. Richards, Jeffrey S. Salowe:
  An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle. 398-407
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• Jason Cong, C. L. Liu:
  Over-the-cell channel routing. 408-418
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• Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong:
  Pad minimization for planar routing of multiple power nets. 419-426
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• K. Iwasaki, F. Arakawa:
  An analysis of the aliasing probability of multiple-input signature registers in the case of a 2^m-ary symmetric channel. 427-438
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• Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
  Probabilistic simulation for reliability analysis of CMOS VLSI circuits. 439-450
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Volume 9, Number 5, May 1990

• Christos A. Papachristou, Anil L. Pandya:
  A design scheme for PLA-based control tables with reduced area and time-delay cost. 453-472
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• Philip A. Wilsey, Subrata Dasgupta:
  A formal model of computer architectures for digital system design environments. 473-486
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• Kiyotaka Yamamura, Kazuo Horiuchi:
  A globally and quadratically convergent algorithm for solving nonlinear resistive networks. 487-499
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• Khushro Shahookar, Pinaki Mazumder:
  A genetic approach to standard cell placement using meta-genetic parameter optimization. 500-511
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• Wing Ning Li, Sartaj Sahni:
  Pull up transistor folding. 512-521
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• Pei-Yung Hsiao, Wu-Shiung Feng:
  Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. 522-536
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• Paul Molitor:
  Constrained via minimization for systolic arrays. 537-542
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• Ernst Rank, Ulrich Weinert:
  A simulation system for diffusive oxidation of silicon: a two-dimensional finite element approach. 543-550
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• Anthony E. Parker, David J. Skellern:
  An improved FET model for computer simulators. 551-553
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• Navneet K. Jain, V. C. Prasad, A. B. Bhattacharyya:
  Delay time sensitivity in nonlinear monotone RC trees. 554-560
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Volume 9, Number 6, June 1990

• Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff:
  Testability analysis of analog systems. 573-583
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• Hans-Joachim Wunderlich:
  Multiple distributions for biased random test patterns. 584-593
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• Rob Dekker, Frans P. M. Beenker, Loek Thijssen:
  A realistic fault model and test algorithms for static random access memories. 567-572
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• Brian T. Murray, John P. Hayes:
  Hierarchical test generation using precomputed tests for modules. 594-603
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• Srinivas Devadas, Hi-Keung Tony Ma:
  Easily testable PLA-based finite state machines. 604-611
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• Bulent I. Dervisoglu:
  Application of scan hardware and software for debug and diagnostics in a workstation environment. 612-620
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• Stephen R. Demba, Ernst Ulrich, Karen Panetta Lentz, David Giramma:
  Experiences with concurrent fault simulation of diagnostic programs. 621-628
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• Kent D. Wilken, John Paul Shen:
  Continuous signature monitoring: low-cost concurrent detection of processor control errors. 629-641
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• S. Chowdhury, J. S. Barkatullah:
  Estimation of maximum currents in MOS IC logic circuits. 642-654
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• Duncan M. Hank Walker, D. S. Nydick:
  DVLASIC: catastrophic fault yield simulation in a distributed processing environment. 655-664
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• D. Y. Cheng, J. T. Deutsch, Robert W. Dutton:
  'Defensive programming' in the rapid development of a parallel scientific program. 665-669
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• Joel W. Gannett:
  SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts. 669-674
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Volume 9, Number 7, July 1990

• W. T. Liou, Jimmy J. M. Tan, Richard C. T. Lee:
  Minimum rectangular partition problem for simple rectilinear polygons. 720-733
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• Michael D. Osterman, Michael G. Pecht:
  Placement for reliability and routability of convectively cooled PWBs. 734-744
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• Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu:
  A fast transistor-chaining algorithm for CMOS cell layout. 781-786
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• Forrest Brewer, Daniel D. Gajski:
  Chippe: a system for constraint driven behavioral synthesis. 681-695
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• Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski:
  Automatic modeling of switch-level networks using partial orders [MOS circuits]. 696-707
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• Robert L. Maziasz, John P. Hayes:
  Layout optimization of static CMOS functional cells. 708-719
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• Shintaro Ushio, Kenji Nishi, Shigeki Kuroda, Kazuhiko Kai, Jun Ueda:
  A fast three-dimensional process simulator OPUS/3D with access to two-dimensional simulation results. 745-751
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• Debashis Bhattacharya, John P. Hayes:
  Designing for high-level test generation. 752-766
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• Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller:
  The analysis of one-dimensional linear cellular automata and their aliasing properties. 767-778
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• Doron Drusinsky-Yoresh:
  Symbolic cover minimization of fully I/O specified finite state machines. 779-781
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• Nripendra N. Biswas:
  On covering distant minterms by the camp algorithm. 786-789
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Volume 9, Number 8, August 1990

• Shiu-Kai Chin, Edward P. Stabler:
  Synthesis of arithmetic hardware using hardware metafunctions. 793-803
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• Nam Ling, Magdy A. Bayoumi:
  Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays. 804-820
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• Matthias Passlack, Manfred Uhle, Horst Elschner:
  Analysis of propagation delays in high-speed VLSI circuits using a distributed line model. 821-826
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• Pierre Roussel-Ragot, Gérard Dreyfus:
  A problem independent parallel implementation of simulated annealing: models and experiments. 827-835
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• Yu Hen Hu, Sao-Jie Chen:
  GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques. 836-845
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• C. D. Maldonado, R. A. Williams:
  A transient analytical model for predicting the redistribution of injected interstitials. 846-855
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• Martin Thurner, Siegfried Selberherr:
  Three-dimensional effects due to the field oxide in MOS devices analyzed with MINIMOS 5. 856-867
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• Nagisa Ishiura, Masyuki Ito, Shuzo Yajima:
  Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. 868-875
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• Michael Demjanenko, Shambhu J. Upadhyaya:
  Yield enhancement of field programmable logic arrays by inherent component redundancy. 876-884
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• Hideo Fujiwara, Tomoo Inoue:
  Optimal granularity of test generation in a distributed system. 885-892
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• Weiwei Mao, Michael D. Ciletti:
  DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation. 893-898
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• Pak K. Chan, Kevin Karplus:
  Computing signal delay in general RC networks by tree/link partitioning. 898-902
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Volume 9, Number 9, September 1990

• Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
  NOVA: state assignment of finite state machines for optimal two-level logic implementation. 905-924
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• Gert Goossens, Jan M. Rabaey, Joos Vandewalle, Hugo De Man:
  An efficient microcode compiler for application specific DSP processors. 925-937
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• Michael C. McFarland, Thaddeus J. Kowalski:
  Incorporating bottom-up design into hardware synthesis. 938-950
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• Resve A. Saleh, Jacob K. White:
  Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. 951-958
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• Bill Lin, A. Richard Newton:
  A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions. 959-969
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• Matthias F. M. Stallmann, Thomas A. Hughes, Wentai Liu:
  Unconstrained via minimization for topological multilayer routing. 970-980
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• Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal:
  Toward massively parallel automatic test generation. 981-994
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• Farid N. Najm, Ibrahim N. Hajj:
  The complexity of fault detection in MOS VLSI circuits. 995-1001
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• Chung-Yu Wu, Ming-Chuen Shiau:
  Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications. 1002-1009
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• F. Joel Ferguson:
  Detection of multiple faults in MOS circuits. 1009-1014
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Volume 9, Number 10, October 1990

• TingTing Hwang, Robert Michael Owens, Mary Jane Irwin:
  Exploiting communication complexity for multilevel logic synthesis. 1017-1027
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• Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili:
  A module generator for optimized CMOS buffers. 1028-1046
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• Evangelos Simoudis:
  Learning redesign knowledge circuit redesign. 1047-1062
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• Patrick Odent, Luc J. M. Claesen, Hugo De Man:
  Acceleration of relaxation-based circuit simulation using a multiprocessor system. 1063-1072
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• Jonathan Rose:
  Parallel global routing for standard cells. 1085-1095
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• Raja Venkateswaran, Pinaki Mazumder:
  A hexagonal array machine for multilayer wire routing. 1096-1112
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• E. Rorris, R. R. O'Brien, F. F. Morehead, R. F. Lever, J. P. Peng, G. R. Srinivasan:
  A new approach to the simulation of the coupled point defects and impurity diffusion. 1113-1122
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• Gregory Munson Yeric, A. F. Tasch Jr., Sanjay K. Banerjee:
  A universal MOSFET mobility degradation model for circuit simulation. 1123-1126
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• Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man:
  Timing verification using statically sensitizable paths. 10723-10784
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Volume 9, Number 11, November 1990

• D. Schroeder:
  Three-dimensional nonequilibrium interface conditions for electron transport at band edge discontinuities. 1136-1140
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• Gerhard K. M. Wachutka:
  Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling. 1141-1149
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• Tarek Shawki, Georges Salmer, Osman El-Sayed:
  2-D simulation of degenerate hot electron transport in MODFETs including DX center trapping. 1150-1163
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• Paolo Lugli:
  The Monte Carlo method for semiconductor device and process modeling. 1164-1176
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• Kenji Taniguchi, Yoshiaki Shibata, Chihiro Hamaguchi:
  Process modeling and simulation: boundary conditions for point defect-based impurity diffusion model. 1177-1183
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• Wolfgang Bergner, Roland Kircher:
  SITAR-an efficient 3-D simulator for optimization of nonplanar trench structures. 1184-1188
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• Martin Thurner, Philipp Lindorfer, Siegfried Selberherr:
  Numerical treatment of nonrectangular field-oxide for 3-D MOSFET simulation. 1189-1197
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• Arokia Nathan, Henry Baltes, Walter Allegretto:
  Review of physical models for numerical simulation of semiconductor microsensors. 1198-1208
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• Peter Lloyd, Heinz K. Dirks, E. James Prendergast, Kishore Singhal:
  Technology CAD for competitive products. 1209-1216
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• Chiaki Takano, Zhiping Yu, Robert W. Dutton:
  A nonequilibrium one-dimensional quantum-mechanical simulation for AlGaAs/GaAs HEMT structures. 1217-1224
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• Valery Axelrad:
  Fourier method modeling of semiconductor devices. 1225-1237
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• Yue-Sun Kuo:
  Representing large cell maps. 1238-1241
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Volume 9, Number 12, December 1990

• Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni:
  Long and short covering edges in combination logic circuits. 1245-1253
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• Angelo Brambilla, Enrico Dallago:
  A circuit-level simulation model of PNPN devices. 1254-1264
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• Jih-Shyr Yih, Pinaki Mazumder:
  A neural network design for circuit partitioning. 1265-1271
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• Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong:
  Layer assignment for multichip modules. 1272-1277
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• Patrick Groeneveld:
  A multiple layer contour-based gridless channel router. 1278-1288
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• Godfried M. Swinkels, Louis J. Hafer:
  Schematic generation with an expert system. 1289-1306
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• Pierre-François Dubois, Alain Puissochet, Anne-Marie Tagant:
  A general and flexible switchbox router: CARIOCA. 1307-1317
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• Charles Chiang, Majid Sarrafzadeh, Chak-Kuen Wong:
  Global routing based on Steiner min-max trees. 1318-1325
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• Gopalakrishnan Vijayan:
  Partitioning logic on graph structures to minimize routing cost. 1326-1334
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• Gabriel M. Silberman, Ilan Y. Spillinger:
  Using functional fault simulation and the difference fault model to estimate implementation fault coverage. 1335-1343
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• Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò:
  Aliasing in signature analysis testing with multiple input shift registers. 1344-1353
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• Richard Booth, Marvin White:
  Simulation of a MOS transistor with spatially nonuniform channel parameters. 1354-1357
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