IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 10

Volume 10, Number 1, January 1991

• Seiyang Yang, Maciej J. Ciesielski:
  Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. 4-12
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• Srinivas Devadas, A. Richard Newton:
  Exact algorithms for output encoding, state assignment, and four-level Boolean minimization. 13-27
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• Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton:
  MUSE: a multilevel symbolic encoding algorithm for state assignment. 28-38
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• Srinivas Devadas, Kurt Keutzer:
  A unified approach to the synthesis of fully testable sequential machines. 39-50
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• Karen A. Bartlett, Gaetano Borriello, Sitaram Raju:
  Timing optimization of multiphase sequential logic. 51-62
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• Giovanni De Micheli:
  Synchronous logic synthesis: algorithms for cycle-time minimization. 63-73
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• Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Retiming and resynthesis: optimizing sequential networks with combinational techniques. 74-84
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• Raul Camposano:
  Path-based scheduling for synthesis. 85-93
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• Randal E. Bryant:
  Formal verification of memory circuits by switch-level simulation. 94-102
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• Dennis L. Young, Jim Teplik, Harrison D. Weed, Neil T. Tracht, Antonio R. Alvarez:
  Application of statistical design and response surface methods to computer-aided VLSI device design II. Desirability functions and Taguchi methods. 103-115
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• Wing K. Luk, Alvar A. Dean:
  Multistack optimization for data-path chip layout. 116-129
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• Tom Smy, R. Niall Tait, Michael J. Brett:
  Ballistic deposition simulation of via metallization using a quasi-three-dimensional model. 130-135
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• Niraj K. Jha:
  Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. 136-143
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Volume 10, Number 2, February 1991

• Teng-Sin Pong, Martin A. Brooke:
  A parasitics extraction and network reduction algorithm for analog VLSI. 145-149
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• Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli:
  A macromodeling algorithm for analog circuits. 150-160
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• Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki:
  A submicrometer MOS transistor I-V model for circuit simulation. 161-170
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• Peter Feldmann, Tuyen V. Nguyen, Stephen W. Director, Ronald A. Rohrer:
  Sensitivity computation in piecewise approximate circuit simulation. 171-183
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• Peter M. Maurer:
  Scheduling blocks of hierarchical compiled simulation of combinational circuits. 184-192
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• Anthony Vannelli:
  An adaptation of the interior point method for solving the global routing problem. 193-203
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• Tai-Tsung Ho, S. Sitharama Iyengar, Si-Qing Zheng:
  A general greedy channel routing algorithm. 204-211
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• Raffaele Costa, Francesco Curatelli, Daniele D. Caviglia, Giacomo M. Bisio:
  Symbolic generation of constrained random logic cells. 220-231
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• Uzi Yoeli:
  A robust channel router. 212-219
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• Emad Fatemi, Joseph W. Jerome, Stanley Osher:
  Solution of the hydrodynamic device model using high-order nonoscillatory shock capturing algorithms. 232-244
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• J. Gregory Rollins:
  Numerical simulator for superconducting integrated circuits. 245-251
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• Bruno Ciciani, Giuseppe Iazeolla:
  A Markov chain-based yield formula for VLSI fault-tolerant chips. 252-259
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• André Ivanov, Corot W. Starke, Vinod K. Agarwal, Wilfried Daehn, Matthias Gruetzner, Tom W. Williams:
  Iterative algorithms for computing aliasing probabilities. 260-265
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• Michiel M. Ligthart, Rudi J. Stans:
  A fault model for PLAs. 265-270
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• Tai-Ching Tuan, Kim-Heng Teo:
  On river routing with minimum number of jogs. 271-273
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• Sarma Sastry, Jen-I Pi:
  Estimating the minimum of partitioning and floorplanning problems. 273-282
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Volume 10, Number 3, March 1991

• Shen-Chuan Tai, M. W. Du, Richard C. T. Lee:
  A transformational approach to synthesizing combinational circuits. 286-295
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• Pranav Ashar, Srinivas Devadas, A. Richard Newton:
  Optimum and heuristic algorithms for an approach to finite state machine decomposition. 296-310
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• Pranav Ashar, Srinivas Devadas, A. Richard Newton:
  Irredundant interacting sequential machines via optimal logic synthesis. 311-325
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• Seung Ho Hwang, A. Richard Newton:
  An efficient verifier for finite state machines. 326-334
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• Per Andersson:
  Design representation in Movie. 335-345
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• Dan Adler:
  Switch-level simulation using dynamic graph algorithms. 346-355
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• Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes, Kurt Antreich:
  GORDIAN: VLSI placement by quadratic programming and slicing optimization. 356-365
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• Mehmet Yanilmaz, Virgil Eveleigh:
  Numerical device modeling for electronic circuit simulation. 366-375
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• Hong June Park, Ping Keung Ko, Chenming Hu:
  A charge sheet capacitance model of short channel MOSFETs for SPICE. 376-389
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• Sarma Sastry, Amitava Majumdar:
  Test efficiency analysis of random self-test of sequential circuits. 390-398
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• Charles H. Stapper:
  Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. 399-406
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• Konstantinos I. Diamantaras, Niraj K. Jha:
  A new transition count method for testing of logic circuits. 407-410
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Volume 10, Number 4, April 1991

• Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  Reduced offsets for minimization of binary-valued functions. 413-426
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• Kurt Keutzer, Sharad Malik, Alexander Saldanha:
  Is redundancy necessary to reduce delay? 427-435
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• Bo-Gwan Kim, Donald L. Dietmeyer:
  Multilevel logic synthesis of symmetric switching functions. 436-446
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• C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen:
  An integrated CAD system for algorithm-specific IC design. 447-463
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• Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu:
  A formal approach to the scheduling problem in high level synthesis. 464-475
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• John H. Chan, Andrei Vladimirescu, Xiao-Chun Gao, Peter Liebmann, John Valainis:
  Nonlinear transformer model for circuit simulation. 476-482
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• James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana S. Richards:
  Distributed genetic algorithms for the floorplan design problem. 483-492
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• Paul Vanoostende, Paul Six, Hugo De Man:
  DARSI: RC data reduction [VLSI simulation]. 493-500
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• Walter Allegretto, Arokia Nathan, Henry Baltes:
  Numerical analysis of magnetic-field-sensitive bipolar devices. 501-511
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• Gennady S. Gildenblat, Cheng-Liang Huang:
  N-channel MOSFET model for the 60-300-K temperature range. 512-518
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• Gerd Krüger:
  A tool for hierarchical test generation. 519-524
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• Youssef Saab, Vasant B. Rao:
  Combinatorial optimization by stochastic evolution. 525-535
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• Khe-Sing The, Martin D. F. Wong, Jason Cong:
  A layout modification approach to via minimization. 536-541
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• Reinhard Erwe, Norio Tanabe:
  Efficient simulation of MOS circuits. 541-544
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• Michele Favalli, Piero Olivo, Bruno Riccò:
  A novel critical path heuristic for fast fault grading. 544-548
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• Keiho Akiyama, Kewal K. Saluja:
  A method of reducing aliasing in a built-in self-test environment. 548-553
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Volume 10, Number 5, May 1991

• C. Leonard Berman, Louise Trevillyan:
  Global flow optimization in automatic logic design. 557-564
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• Genhong Ruan, Jiri Vlach, James A. Barby, Ajoy Opal:
  Analog functional simulator for multilevel systems. 565-576
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• Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici:
  An accurate analytical delay model for BiCMOS driver circuits. 577-588
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• Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin:
  A recursive technique for computing delays in series-parallel MOS transistor circuits. 589-595
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• Wayne Bower, Carl Seaquist, Wayne Wolf:
  A framework for industrial layout generators. 596-603
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• Krishna P. Belkhale, Prithviraj Banerjee:
  Parallel algorithms for VLSI circuit extraction. 604-618
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• Shinji Odanaka, Akira Hiroki, Kikuyo Ohe, Kaori Moriyama, Hiroyuki Umimoto:
  SMART-II: a three-dimensional CAD model for submicrometer MOSFET's. 619-628
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• Hong June Park, Ping Keung Ko, Chenming Hu:
  A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. 629-642
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• Richard B. Fair, Carl L. Gardner, Michael J. Johnson, Stephen W. Kenkel, Donald J. Rose, J. E. Rose, Ravi Subrahmanyan:
  Two-dimensional process simulation using verified phenomenological models. 643-651
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• Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
  Test generation and verification for highly sequential circuits. 652-667
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• Giuseppe Acciani, D. Congedo, Bruno Dilecce:
  Improving the computational efficiency of the tree relaxation method for an iterative solution of linear circuit equations. 668-670
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• H. Y. Chen, Sung-Mo Kang:
  A new circuit optimization technique for high performance CMOS circuits. 670-677
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• Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò:
  Fault simulation of unconventional faults in CMOS circuits. 677-682
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Volume 10, Number 6, June 1991

• C. Y. Roger Chen, Michael Z. Moricz:
  A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms. 685-697
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• James Daniell, Stephen W. Director:
  An object oriented approach to CAD tool control [VLSI]. 698-713
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• Paul F. Cox, Richard Burch, Dale E. Hocevar, Ping Yang, Berton D. Epler:
  Direct circuit simulation algorithms for parallel processing [VLSI]. 714-725
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• David M. Lewis:
  A hierarchical compiled code event-driven logic simulator. 726-737
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• Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici:
  SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. 738-747
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• Jörg Heisterman, Thomas Lengauer:
  The efficient solution of integer programs for hierarchical global routing. 748-753
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• Kamal Chaudhary, Peter Robinson:
  Channel routing by sorting. 754-760
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• Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen:
  An analytical approach to floorplan design and optimization. 761-769
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• Bradley S. Carlson, C. Y. Roger Chen, Uminder Singh:
  Optimal cell generation for dual independent layout styles. 770-782
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• Dorothy E. Setliff, Rob A. Rutenbar:
  On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF. 783-801
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• Yoshihiko Hirai, Sadafumi Tomida, Kazushi Ikeda, Masaru Sasago, Masayuki Endo, Sigeru Hayama, Noboru Nomura:
  Three-dimensional resist process simulator PEACE (photo and electron beam lithography analyzing computer engineering system). 802-807
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• Paul A. Gough, Martin K. Johnson, Philip Walker, Henk Hermans:
  An integrated device design environment for semiconductors. 808-821
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• J. H. Smith, Kenneth M. Steer, Timothy F. Miller, Stephen J. Fonash:
  Numerical modeling of two-dimensional device structures using Brandt's multilevel acceleration scheme: application to Poisson's equation. 822-824
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Volume 10, Number 7, July 1991

• David W. Knapp, Alice C. Parker:
  The ADAM design planning engine. 829-846
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• Elizabeth D. Lagnese, Donald E. Thomas:
  Architectural partitioning for system level synthesis of integrated circuits. 847-860
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• Chandramouli Visweswariah, Ronald A. Rohrer:
  Piecewise approximate circuit simulation. 861-870
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• Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar:
  Massively parallel switch-level simulation: a feasibility study. 871-894
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• K. K. Low, Stephen W. Director:
  A new methodology for the design centering of IC fabrication processes. 895-903
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• Walter Guggenbühl, Guy Morbach, Michael Schaller:
  Simulation lossless symmetrical three conductor systems. 904-910
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• Yen-Chuen Wei, Chung-Kuan Cheng:
  Ratio cut partitioning for hierarchical designs. 911-921
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• Larry G. Jones:
  Fast batch incremental netlist compilation hierarchical schematics. 922-931
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• Andres R. Takach, Niraj K. Jha:
  Easily testable gate-level and DCVS multipliers. 932-942
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• Sreejit Chakravarty, Xin He, S. S. Ravi:
  Minimum area layout of series-parallel transistor networks is NP-hard. 943-949
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• Jiri Vlach, James A. Barby, Anthony Vannelli, T. Talkhan, C.-J. Richard Shi:
  Group delay as an estimate of delay in logic. 949-953
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Volume 10, Number 8, August 1991

• Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh:
  Consistency checking and optimization of macromodels. 957-967
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• Silvano Gai, Pier Luca Montessoro:
  The fault dropping problem in concurrent event-driven simulation. 968-971
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• Jason Cong, C. L. Liu:
  On the k-layer planar subset and topological via minimization problems. 972-981
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• Yoichi Shiraishi, Jun'ya Sakemi, Kazuyuki Fukuda:
  Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout. 982-993
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• Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
  LiB: a CMOS cell compiler. 994-1005
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• Hany L. Abdel-Malek, Abdel-Karim S. O. Hassan:
  The ellipsoidal technique for design centering and region approximation. 1006-1014
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• Michael J. Van der Tol, Savvas G. Chamberlain:
  Buried-channel MOSFET model for SPICE. 1015-1035
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• Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
  Design of robustly testable combinational logic circuits. 1036-1048
  Electronic Edition (link) BibTeX
• Andrzej J. Strojwas, Stephen W. Director:
  An efficient algorithm for parametric fault simulation of monolithic IC's. 1049-1058
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• C. Leonard Berman:
  Circuit width, register allocation, and ordered binary decision diagrams. 1059-1066
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• Min-Siang Lin, Houng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin:
  Channel density reduction by routing over the cells. 1067-1071
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• Giuseppe Caruso:
  Near optimal factorization of Boolean functions. 1072-1078
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• Pak K. Chan:
  Comments on `Asymptotic waveform evaluation for timing analysis'. 1078-1079
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Volume 10, Number 9, September 1991

• Roberto Guerrieri, Karim H. Tadros, John K. Gamelin, Andrew R. Neureuther:
  Massively parallel algorithms for scattering in optical lithography. 1091-1100
  Electronic Edition (link) BibTeX
• T. Thurgate:
  Segment-based etch algorithm and modeling. 1101-1109
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• Xiaowei Tian, Andrzej J. Strojwas:
  Numerical integral method for diffusion modeling. 1110-1124
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• Mark E. Law:
  Parameters for point-defect diffusion and recombination. 1125-1131
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• Ke-Chih Wu, Goodwin R. Chin, Robert W. Dutton:
  A STRIDE towards practical 3-D device simulation-numerical and visualization considerations. 1132-1140
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• Paolo Ciampolini, Anna Pierantoni, Giorgio Baccarani:
  Efficient 3-D simulation of complex structures. 1141-1149
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• Duane S. Boning, Michael L. Heytens, Alexander S. Wong:
  The intertool profile interchange format: an object-oriented approach [semiconductor technology CAD/CAM]. 1150-1156
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• Alexander S. Wong, Andrew R. Neureuther:
  The intertool profile interchange format: a technology CAD environment approach [semiconductor technology]. 1157-1162
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• Mark R. Simpson:
  PRIDE: an integrated design environment for semiconductor device simulation. 1163-1174
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• Karl H. Bach, Heinz K. Dirks, Bernd Meinerzhagen, Walter L. Engl:
  A new nonlinear relaxation scheme for solving semiconductor device equations. 1175-1186
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• Carl L. Gardner, Paul J. Lanzkron, Donald J. Rose:
  A parallel block iterative method for the hydrodynamic device model. 1187-1192
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• Tai-Yu Chou, Zoltan J. Cendes:
  Tangential vector finite elements for semiconductor device simulation. 1193-1200
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• Donald M. Webber, Eric Tomacruz, Roberto Guerrieri, Toru Toyabe, Alberto L. Sangiovanni-Vincentelli:
  A massively parallel algorithm for three-dimensional device simulation. 1201-1209
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Volume 10, Number 10, October 1991

• Gernot Heiser, Claude Pommerell, Jürgen Weis, Wolfgang Fichtner:
  Three-dimensional numerical semiconductor device simulation: algorithms, architectures, results. 1218-1230
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• Paolo Conti, Nancy Hitschfeld-Kahler, Wolfgang Fichtner:
  Omega-an octree-based mixed element grid allocator for the simulation of complex 3-D device structures. 1231-1241
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• Zsolt Miklós Kovács-Vajna, Massimo Rudan:
  Boundary fitted coordinated generation for device analysis on composite and complicated geometries. 1242-1250
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• Josef F. Burgler, William M. Coughran Jr., Wolfgang Fichtner:
  An adaptive grid refinement strategy for the drift-diffusion equations. 1251-1258
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• William M. Coughran Jr., Mark R. Pinto, R. Kent Smith:
  Adaptive grid generation for VSLI device simulation. 1259-1275
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• Franco Venturi, Enrico Sangiorgi, Rosella Brunetti, Wolfgang Quade, Carlo Jacoboni, Bruno Riccò:
  Monte Carlo simulations of high energy electrons and holes in Si-n-MOSFET's. 1276-1286
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• Wolfgang Quade, Massimo Rudan, Eckehard Scholl:
  Hydrodynamic simulation of impact-ionization effects in p-n junctions. 1287-1294
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• Kazushige Horio, Yasuji Fuseya, Hiroyuki Kusuki, Hisayoshi Yanai:
  Simplified simulations of GaAs MESFET's with semi-insulating substrate compensated by deep levels. 1295-1302
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• Ralph-Michael Kling, Prithviraj Banerjee:
  Empirical and theoretical studies of the simulated evolution method applied to standard cell placement. 1303-1315
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• Janusz Rajski, Jerzy Tyszer:
  On the diagnostic properties of linear feedback shift registers. 1316-1322
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• Karl Fuchs, Franz Fink, Michael H. Schulz:
  DYNAMITE: an efficient automatic test pattern generation system for path delay faults. 1323-1335
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Volume 10, Number 11, November 1991

• Reinaldo A. Bergamaschi:
  SKOL: a system for logic synthesis and technology mapping. 1342-1355
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• Robert P. Kurshan, Kenneth L. McMillan:
  Analysis of digital circuits through symbolic reduction. 1356-1371
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• Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
  An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. 1372-1381
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• Kuo-Feng Liao, Majid Sarrafzadeh:
  Boundary single-layer routing with movable terminals. 1382-1391
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• Ioannis G. Tollis:
  A new approach to wiring layouts. 1392-1400
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• Jason Cong:
  Pin assignment with global routing for general cell designs. 1401-1412
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• Yang Cai, Martin D. F. Wong:
  Optimal channel pin assignment. 1413-1424
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• Martin D. F. Wong, Mohankumar Guruswamy:
  Channel ordering for VLSI layout with rectilinear modules. 1425-1431
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• Zhong-Yi Zhao, Qi-Ming Zhang, Gen-Lin Tan, J. M. (Jimmy) Xu:
  A new preconditioner for CGS iteration in solving large sparse nonsymmetric linear equations in semiconductor device simulation. 1432-1440
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• Craig MacInnes:
  The use of small pivot perturbation in circuit analysis. 1441-1446
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• Keith Nabors, Jacob K. White:
  FastCap: a multipole accelerated 3-D capacitance extraction program. 1447-1459
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• Barry M. Pangrle:
  On the complexity of connectivity binding. 1460-1465
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• Jacob Savir, Paul H. Bardell:
  Partitioning of polynomial tasks: test generation, an example. 1465-1468
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Volume 10, Number 12, December 1991

• Srinivas Devadas:
  Optimizing interacting finite state machines using sequential don't cares. 1473-1484
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• Yang Cai, Martin D. F. Wong:
  Channel/switchbox definition for VLSI building-block layout. 1485-1493
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• Gopalakrishnan Vijayan, Ren-Song Tsay:
  A new method for floor planning using topological constraint reduction. 1494-1501
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• Chung-Kuan Cheng, Yen-Chuen A. Wei:
  An improved two-way partitioning algorithm with stable performance [VLSI]. 1502-1511
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• A. R. Boothroyd, Stan W. Tarasewicz, Cezary Slaby:
  MISNAN-a physically based continuous MOSFET model for CAD applications. 1512-1529
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• Yao-Tsung Tsai, Timothy A. Grotjohn:
  Small-signal analysis of MESFET including the energy conservation equation. 1530-1533
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• Gyo-Young Jin, Young-June Park, Hong-Shick Min:
  Mixed particle Monte Carlo method for deep submicron semiconductor device simulator. 1534-1541
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• Srinivas Patil, Prithviraj Banerjee:
  Performance trade-offs in a parallel test generation/fault simulation environment. 1542-1558
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• Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
  Single-fault fault-collapsing analysis in sequential logic circuits. 1559-1568
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• Doron Drusinsky-Yoresh:
  A state assignment procedure for single-block implementation of state charts. 1569-1576
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• Doron Drusinsky-Yoresh:
  Decision problems for interacting finite state machines. 1576-1579
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• Yie He, Guoxiang Cao:
  A generalized Scharfetter-Gummel method to eliminate crosswind effects [semiconduction device modeling]. 1579-1582
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• Yoshiyasu Takefuji, Kuo Chun Lee, Yong B. Cho:
  Comments on 'O(n²) algorithms for graph planarization'. 1582-1583
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