IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 7

Volume 7, Number 1, January 1988

• H. Fujiwara:
  A design of programmable logic arrays with random pattern-testability. 5-10
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• Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs:
  Methodologies for testing embedded content addressable memories. 11-20
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• Shek-Wayne Chan, Chin-Long Wey:
  The design of concurrent error diagnosable systolic arrays for band matrix multiplications. 21-37
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• Larry Carter, Leendert M. Huisman, Tom W. Williams:
  TRIM: testability range by ignoring the memory. 38-49
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• Dick L. Liu, Edward J. McCluskey:
  Design of large embedded CMOS PLAs for built-in self-test. 50-59
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• Shambhu J. Upadhyaya, Kewal K. Saluja:
  A new approach to the design of built-in self-testing PLAs for high fault coverage. 60-67
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• Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner:
  Probability models for pseudorandom test sequences. 68-74
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• Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
  Bounds and analysis of aliasing errors in linear feedback shift registers. 75-83
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• K. Iwasaki:
  Analysis and proposal of signature circuits for LSI testing. 84-90
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• Laung-Terng Wang, Edward J. McCluskey:
  Hybrid designs generating maximum-length sequences. 91-99
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• Joseph L. A. Hughes:
  Multiple fault detection using single fault test sets. 100-108
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• Niraj K. Jha:
  Testing for multiple faults in domino-CMOS logic circuits. 109-116
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• Ronald J. Cosentino:
  Concurrent error correction in systolic architectures. 117-125
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• Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert:
  SOCRATES: a highly efficient automatic test pattern generation system. 126-137
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• Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland:
  Logic design verification via test generation. 138-148
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Volume 7, Number 2, February 1988

• Joachim Pelka, K. P. Muller, Hermann Mader:
  Simulation of dry etch processes by COMPOSITE. 154-159
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• K. Lee, Andrew R. Neureuther:
  SIMPL-2: (SIMulated Profiles from the Layout-Version 2). 160-167
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• Francisco A. Leon:
  Numerical modeling of glass flow and spin-on planarization. 168-173
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• Gerhard Hobler, Siegfried Selberherr:
  Two-dimensional modeling of ion implantation induced point defects. 174-180
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• Mark E. Law, Robert W. Dutton:
  Verification of analytic point defect models using SUPREM-IV [dopant diffusion]. 181-190
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• Michael R. Kump, Robert W. Dutton:
  The efficient simulation of coupled point defect and impurity diffusion. 191-204
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• Ettore Landi, Paul G. Carey, Thomas W. Sigmon:
  Numerical simulation of the gas immersion laser doping (GILD) process in silicon. 205-214
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• Thye-Lai Tung, J. Connor, Dimitri A. Antoniadis:
  A boundary element method for modeling viscoelastic flow in thermal oxidation. 215-224
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• Mayumi Hirose, Jiro Yoshida, Nobuyuki Toyoda:
  An improved two-dimensional simulation model (MEGA) for GaAs MESFET applicable to LSI design. 225-230
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• Alessandro Forghieri, Roberto Guerrieri, Paolo Ciampolini, Antonio Gnudi, Massimo Rudan, Giorgio Baccarani:
  A new discretization strategy of the semiconductor equations comprising momentum and energy balance. 231-242
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• Ross A. Williams, Deva N. Pattanayak:
  ADAM: a two dimensional, two-carrier MOSFET simulator based on generalized stream functions. 243-250
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• Christian A. Ringhofer, Christian Schmeiser:
  A modified Gummel method for the basic semiconductor device equations. 251-253
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• Masaaki Tomizawa, Kiyoyuki Yokoyama, Akira Yoshii:
  Nonstationary carrier dynamics in quarter-micron Si MOSFETs. 254-258
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• Enrico Sangiorgi, Bruno Riccò, Franco Venturi:
  MOS²: an efficient MOnte Carlo Simulator for MOS devices. 259-271
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• Antonio R. Alvarez, Behrooz L. Abdi, Dennis L. Young, Harrison D. Weed, Jim Teplik, Eric R. Herald:
  Application of statistical design and response surface methods to computer-aided VLSI device design. 272-288
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• Mario Pinto-Guedes, Philip C. Chan:
  A circuit simulation model for bipolar-induced breakdown in MOSFET. 289-294
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• Erich Barke:
  Line-to-ground capacitance calculation for VLSI: a comparison. 295-298
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• Vered Marash, Robert W. Dutton:
  Methodology for submicron device model development. 299-306
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• William M. Coughran Jr., Mark R. Pinto, R. Kent Smith:
  Computation of steady-state CMOS latchup characteristics. 307-323
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Volume 7, Number 3, March 1988

• Sunil D. Sherlekar, P. S. Subramanian:
  Conditionally robust two-pattern tests and CMOS design for testability. 325-332
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• Sheldon B. Akers:
  A parity bit signature for exhaustive testing. 333-338
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• Hung Chi Lai, Saburo Muroga:
  Design of MOS networks in single-rail input logic for incompletely specified functions. 339-345
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• Hans-Jorg Mathony, Utz G. Baitinger:
  CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits. 346-355
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• Nohbyung Park, Alice C. Parker:
  Sehwa: a software package for synthesis of pipelines from behavioral specifications. 356-370
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• Shmuel Wimer, Israel Koren:
  Analysis of strategies for constructive general block placement. 371-377
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• Amir Alon, Uri M. Ascher:
  Model and solution strategy for placement of rectangular blocks in the Euclidean plane. 378-386
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• Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic:
  Parallel standard cell placement algorithms with quality equivalent to simulated annealing. 387-396
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• Rob A. Rutenbar, Daniel E. Atkins:
  Systolic routing hardware: performance evaluation and optimization. 397-410
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• Musaravakkam S. Krishnan, John P. Hayes:
  A normalized-area measure for VLSI layouts. 411-419
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• Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara:
  Minimization of the number of layers for single row routing with fixed street capacity. 420-424
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• R. J. McDonald, Jerry G. Fossum:
  High-voltage device modeling for SPICE simulation of HVIC's. 425-432
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Volume 7, Number 4, April 1988

• J.-N. Song, Y.-K. Chen:
  Two-stage channel routing for CMOS gate arrays. 439-450
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• Wayne Wolf, Robert G. Mathews, John A. Newkirk, Robert W. Dutton:
  Algorithms for optimizing, two-dimensional symbolic layout compaction. 451-466
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• Sartaj K. Sahni, San-Yuan Wu:
  Two NP-hard interchangeable terminal problems. 467-472
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• Surendra Nahar, Sartaj K. Sahni:
  Fast algorithm for polygon decomposition. 473-483
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• Allan Silburt, A. R. Boothroyd, M. Digiovanni:
  Automated parameter extraction and modeling of the MOSFET below threshold. 484-488
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• Christian H. Corbex, Anne F. Gerodelle, Serge P. Martin, Alain R. Poncet:
  Data structuring for process and device simulations. 489-500
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• William Nye, David C. Riley, Alberto L. Sangiovanni-Vincentelli, André L. Tits:
  DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. 501-519
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• Bing J. Sheu, Wen-Jay Hsu, P. K. Ko:
  An MOS transistor charge model for VLSI design. 520-527
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• Chin-Long Wey:
  On yield consideration for the design of redundant programmable logic arrays. 528-535
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• M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia:
  Allocation of multiport memories in data path synthesis. 536-540
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• Jerry G. Fossum, Surya Veeraraghavan, Dan Fitzpatrick:
  Model selection for SOI MOSFET circuit simulation. 541-544
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Volume 7, Number 5, May 1988

• Albert Seidl, Helmut Klose, Milos Svoboda, Joachim Oberndorfer, Wolfgang Rösner:
  CAPCAL-a 3-D capacitance solver for support of CAD systems. 549-556
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• James A. Barby, Jiri Vlach, Kishore Singhal:
  Polynomial splines for MOSFET model approximation. 557-566
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• Ernst Christen, Jiri Vlach:
  NETOPT-a program for multiobjective design of linear networks. 567-577
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• Chang G. Hwang, Robert W. Dutton:
  Hot carrier transport effect in Schottky-barrier diode grown by MBE. 578-583
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• John P. Robinson, Nirmal R. Saxena:
  Simultaneous signature and syndrome compression. 584-589
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• Gopal Gupta, Niraj K. Jha:
  A universal test set for CMOS circuits. 590-597
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• André Ivanov, Vinod K. Agarwal:
  Dynamic testability measures for ATPG. 598-608
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• Wei-Kang Huang, Fabrizio Lombardi:
  On an improved design approach for C-testable orthogonal iterative arrays. 609-615
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• Gary D. Hachtel, Reily M. Jacoby:
  Verification algorithms for VLSI synthesis. 616-640
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• Gregory J. Fisher:
  An enhanced power meter for SPICE2 circuit simulation. 641-643
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Volume 7, Number 6, June 1988

• Dale E. Hocevar, Paul F. Cox, Ping Yang:
  Parametric yield optimization for MOS circuit blocks. 645-658
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• Genhong Ruan, Jiri Vlach, James A. Barby:
  Current-limited switch-level timing simulator for MOS logic networks. 659-667
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• Bernhard E. Boser, Klaus-Peter Karmann, Horst Martin, Bruce A. Wooley:
  Simulating and testing oversampled analog-to-digital converters. 668-674
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• Shinji Odanaka, Hiroyuki Umimoto, Mutsuko Wakabayashi, Hideya Esaki:
  SMART-P: rigorous three-dimensional process simulator on a supercomputer. 675-683
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• James P. Cohoon, Patrick L. Heck:
  BEAVER: a computational-geometry-based tool for switchbox routing. 684-697
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• Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma:
  Techniques for multilayer channel routing. 698-712
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• Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton:
  On the verification of sequential machines at differing levels of abstraction. 713-722
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• Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
  Multi-level logic minimization using implicit don't cares. 723-740
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Volume 7, Number 7, July 1988

• Steven G. Duvall:
  An interchange format for process and device simulation. 741-754
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• Roberto Guerrieri, Andrew R. Neureuther:
  Simulation of microcrack effects in dissolution of positive resist exposed by X-ray lithography. 755-764
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• Sun Young Hwang, Tom Blank, Kiyoung Choi:
  Fast functional simulation: an incremental approach. 765-774
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• Corrado Pedron, André Stauffer:
  Analysis and synthesis of combinational pass transistor circuits. 775-786
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• Salim U. Chowdhury, Melvin A. Breuer:
  Optimum design of IC power/ground nets subject to reliability constraints. 787-796
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• Takao Asano:
  Generalized Manhattan path algorithm with applications. 797-804
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• Shervin Hojat, Richard Y. Kain:
  On the simplification of a placement problem. 805-812
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• Henry Cox, Janusz Rajski:
  A method of fault analysis for test generation and fault diagnosis. 813-833
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Volume 7, Number 8, August 1988

• Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
  SLS-a fast switch-level simulator [for MOS]. 838-849
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• K. Garwacki:
  Extraction of BJT model parameters using optimization method. 850-854
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• Jan J. H. van der Biesen, Toru Toyabe:
  Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices. 855-861
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• J. Gregory Rollins, John Choma Jr.:
  Mixed-mode PISCES-SPICE coupled circuit and device solver. 862-867
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• Youn-Long Lin, Daniel D. Gajski:
  LES: a layout expert system. 868-876
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• Richard I. Hartley, Jeffrey R. Jasica:
  Behavioral to structural translation in a bit-serial silicon compiler. 877-886
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• Chidchanok Lursinsap, Daniel D. Gajski:
  A technique for pull-up transistor folding. 887-896
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• Peter M. Maurer, Alexander D. Schapira:
  A logic-to-logic comparator for VLSI layout verification. 897-907
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• Edmund M. Clarke, Yulin Feng:
  Escher-a geometrical layout system for recursively defined circuits. 908-918
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• Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront:
  On using signature registers as pseudorandom pattern generators in built-in self-testing. 919-928
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• Rex E. Lowther:
  The solution of a numerical problem encountered when adding a mobility model to a finite-element device simulator. 929-930
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Volume 7, Number 9, September 1988

• Sarma Sastry, Melvin A. Breuer:
  Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. 933-946
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• Wei Shu, Min-You Wu, S. M. Kang:
  Improved net merging method for gate matrix layout. 947-951
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• Shiuh-Wuu Lee, Robert C. Rennick:
  A compact IGFET model-ASIM. 952-975
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• Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli:
  A new aggregation technique for the solution of large systems of algebraic equations [IC simulation]. 976-986
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• Andrew W. Appel:
  Simulating digital circuits with one bit per wire. 987-993
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• Christer Svensson, Robert Tjärnström:
  Switch-level simulation and the pass transistor EXOR gate. 994-997
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• Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu:
  Device and circuit simulation interface for an integrated VLSI design environment. 998-1004
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• Silvano Gai, Pier Luca Montessoro, Fabio Somenzi:
  MOZART: a concurrent multilevel simulator. 1005-1016
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• D. Y. Cheng, Chang G. Hwang, Robert W. Dutton:
  PISCES-MC: a multiwindow, multimethod 2-D device simulator. 1017-1026
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Volume 7, Number 10, October 1988

• Albertus J. Kemp, Jacobus A. Pretorius, Willem Smit:
  The generation of a mesh for resistance calculation in integrated circuits. 1029-1037
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• Sepuan Yu, A. F. Franz, T. G. Mihran:
  A physical parametric transistor model for CMOS circuit simulation. 1038-1052
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• Tian-Shen Tang, M. A. Styblinski:
  Yield optimization for nondifferentiable density functions using convolution techniques. 1053-1067
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• Laung-Terng Wang, Edward J. McCluskey:
  Circuits for pseudoexhaustive test pattern generation. 1068-1080
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• Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  Test generation for sequential circuits. 1081-1093
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• Jason Cong, Martin D. F. Wong, C. L. Liu:
  A new approach to three- or four-layer channel routing. 1094-1104
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• Micaela Serra, Jon C. Muzio:
  Space compaction for multiple-output circuits. 1105-1113
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• Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli:
  An algorithm for functional reconfiguration of fixed-size arrays. 1114-1118
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• Wolfgang O. Budde:
  Modular testprocessor for VLSI chips and high-density PC boards. 1118-1124
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Volume 7, Number 11, November 1988

• Roberto Guerrieri, Alberto L. Sangiovanni-Vincentelli:
  Three-dimensional capacitance evaluation on a Connection Machine. 1125-1133
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• David M. Lewis:
  Hardware accelerators for timing simulation of VLSI digital circuits. 1134-1149
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• Gen-Lin Tan, Shao-Wei Pan, Walter H. Ku, An-Jui Shey:
  ADIC-2.C a general-purpose optimization program suitable for integrated circuit design applications using the pseudo objective function substitution method (POSM). 1150-1163
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• Claudio Lombardi, Stefano Manzini, Antonio Saporito, Massimo Vanzi:
  A physically based mobility model for numerical simulation of nonplanar devices. 1164-1171
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• Paolo Camurati, P. Gianoglio, R. Gianoglio, Paolo Prinetto:
  ESTA: an expert system for DFT rule verification. 1172-1180
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• F. Joel Ferguson, John Paul Shen:
  A CMOS fault extractor for inductive fault analysis. 1181-1194
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• Jin-fuw Lee:
  A new framework of design rules for compaction of VLSI layouts. 1195-1204
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• Hwan Gue Cho, C. M. Kyung:
  A heuristic standard cell placement algorithm using constrained multistage graph model. 1205-1214
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• Sharon R. Perkins, Tom Rhyne:
  An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function. 1215-1218
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Volume 7, Number 12, December 1988

• Zhen-qiu Ning, Patrick Dewilde:
  SPIDER: capacitance modelling for VLSI interconnections. 1221-1228
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• Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro:
  MOSTSM: a physically based charge conservative MOSFET model. 1229-1236
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• Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen:
  Macromodeling CMOS circuits for timing simulation. 1237-1249
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• Kewal K. Saluja, Rajiv Sharma, Charles R. Kime:
  A concurrent testing technique for digital circuits. 1250-1260
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• Y. You, John P. Hayes:
  Implementation of VLSI self-testing by regularization. 1261-1271
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• Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa:
  A macrocell approach for VLSI processor design. 1272-1277
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• Yen-Tai Lai, Sany M. Leinwand:
  Algorithms for floorplan design via rectangular dualization. 1278-1289
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• Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
  MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. 1290-1300
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• Leo R. Piotrowski:
  An improved Spice2 Zener diode model for soft-region simulation capability. 1301-1303
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