| 1997 |
|---|
| 11 | EE | Najmi T. Jarwala:
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules.
J. Electronic Testing 10(1-2): 77-86 (1997) |
| 1996 |
|---|
| 10 | EE | Najmi T. Jarwala,
Paul W. Rutkowski,
Shianling Wu,
Chi W. Yau:
Lessons Learned from Practical Applications of BIST/B-S Technology.
Asian Test Symposium 1996: 251-257 |
| 9 | EE | J. El-Ziq,
Najmi T. Jarwala,
Niraj K. Jha,
Peter Marwedel,
Christos A. Papachristou,
Janusz Rajski,
John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw!
VTS 1996: 506-507 |
| 8 | | Bernd Könemann,
Ben Bennetts,
Najmi T. Jarwala,
Benoit Nadeau-Dostie:
Built-In Self-Test: Assuring System Integrity.
IEEE Computer 29(11): 39-45 (1996) |
| 1995 |
|---|
| 7 | | Wuudiann Ke,
Duy Le,
Najmi T. Jarwala:
A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus.
ITC 1995: 789-796 |
| 1994 |
|---|
| 6 | | Najmi T. Jarwala:
Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules.
ITC 1994: 446-455 |
| 1992 |
|---|
| 5 | | Najmi T. Jarwala,
Paul Stiling,
Enn Tammaru,
Chi W. Yau:
A Framework for Boundary-Scan Based System Test Diagnosis.
ITC 1992: 993-998 |
| 1991 |
|---|
| 4 | | Najmi T. Jarwala,
Chi W. Yau:
Achieving Board-Level BIST Using the Boundary-Scan Master.
ITC 1991: 649-658 |
| 1989 |
|---|
| 3 | | Najmi T. Jarwala,
Chi W. Yau:
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects.
ITC 1989: 63-70 |
| 2 | | Najmi T. Jarwala,
Chi W. Yau:
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects.
ITC 1989: 71-77 |
| 1988 |
|---|
| 1 | | Najmi T. Jarwala,
Dhiraj K. Pradhan:
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
IEEE Trans. Computers 37(10): 1235-1250 (1988) |
