ITC 1989:
Washington,
D.C.,
USA
Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989.
IEEE Computer Society 1989 BibTeX
@proceedings{DBLP:conf/itc/1989,
title = {Proceedings International Test Conference 1989, Washington, D.C.,
USA, August 1989},
booktitle = {ITC},
publisher = {IEEE Computer Society},
year = {1989},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 2:
Sequential ATPG
Session 3:
Boundary Scan Algorithms and Implementation
Session 4:
Systems Test I
Session 5:
Mixed Signal Testing I
Session 6:
Delay Test Generation
Session 7:
Boundary Scan in Board and Prototype Testing Today
Session 8:
Coupling,
Distribution and Probes
Session 9:
Mixed Signal Testing II
Session 10:
Panel Session,
Design and Test in the University
Session 11:
Panel Session,
SPC/TQM What It Is ... What It Is Not
Session 13:
Pattern Generation for Built-In-Self-Test
Session 14:
Systems Test II
Session 15:
Practical Quality Isues- Today
Session 16:
Design for Test of VLSI Memories
Session 17:
Topics in Signature Analysis
Session 18:
Testability Analysis
Session 19:
Leading Edge Quality Issues
Session 20:
Concepts in Memory Testing
Session 21:
Hierarichical Test Generation
Session 22:
Synthesis for Testability
Session 23:
Process Improvement Aided by New Analytic Approaches
Session 24:
Logic ATE Architecture
- Gary J. Lesmeister:
The Linear Array Systolic Tester (LAST).
543-549 BibTeX
- Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater:
Low Cost Testing of High Density Logic Components.
550-557 BibTeX
- Shuji Kikuchi, Yoshihiko Hayashi, Takashi Matsumoto, Ryozou Yoshino, Ryuichi Takagi:
A 250 MHz Shared-Resource VLSI Test System with High Pin Count and Memory Test Capability.
558-566 BibTeX
Session 25:
Panel Session,
Random Vectors in External Testing:
Free Lunch or Hidden Costs?
Session 26:
Test Software
Session 27:
Managing the Cost or VLSI Testing
Session 28:
Advanced Test Solutions In Today`s VLSI Processors
Session 29:
Physical Defects ub VLSI Chips
Session 30:
Design For Testability
Session 31:
Board Test I- Test Development and Applications
Session 32:
Advances in Fault Simulation
Session 33:
Practical Considerations in BIST Implementation
Session 34:
Board Test II- Architecture and Accuracy
Session 35:
New Topics in ATPG
Session 36:
CAE and Workstations
Session 37:
Drivers,
Detectors and Sensitivities.
Session 38:
The Economics of Design-for-Testability
Session 39:
ASIC Products-The Test Challenge
Session 40:
E-Beam Update
Poster Session
- Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò:
CMOS Design for Improved IC Testability.
934 BibTeX
- John C. Chan, Baxter F. Womack:
Diagnostics Based on Fault Signature.
935 BibTeX
- Piero Olivo, Maurizio Damiani, Bruno Riccò:
On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing.
936 BibTeX
- R. Ernst, S. Sutarwala, J.-Y. Jou:
TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools.
937 BibTeX
- David Haupert, Fu-Gin Chen, David Lee:
VLSI Package Reliability Risk Due to Accelerated Environmental Testing.
938 BibTeX
Copyright © Sat May 16 23:26:41 2009
by Michael Ley (ley@uni-trier.de)
