VTS 2004:
Napa Valley,
CA,
USA
22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA.
IEEE Computer Society 2004, ISBN 0-7695-2134-7 BibTeX
Defect-Oriented Testing
- Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer:
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets.
9-15
Electronic Edition (link) BibTeX
- Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra:
ELF-Murphy Data on Defects and Test Sets.
16-22
Electronic Edition (link) BibTeX
- Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo:
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor.
23-30
Electronic Edition (link) BibTeX
Delay Testing
- Manish Sharma, Janak H. Patel:
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
31-36
Electronic Edition (link) BibTeX
- Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi:
A Statistical Fault Coverage Metric for Realistic Path Delay Faults.
37-42
Electronic Edition (link) BibTeX
- Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger:
Delay Defect Screening using Process Monitor Structures.
43-52
Electronic Edition (link) BibTeX
Current Based Testing
Test Data Compression and Low-Speed ATE
Pattern Debug,
Yield Analysis and FPGA Testing
Memory Testing I
MEMs Testing and FPGA Testing
Low-Voltage and Thermal Testing
- Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker:
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
171-178
Electronic Edition (link) BibTeX
- Josep Altet, Antonio Rubio, M. Amine Salhi, J. L. Gálvez, Stefan Dilhaire, Ashish Syal, André Ivanov:
Sensing temperature in CMOS circuits for Thermal Testing.
179-184
Electronic Edition (link) BibTeX
- Ethan Long, W. Robert Daasch, Robert Madge, Brady Benware:
Detection of Temperature Sensitive Defects Using ZTC.
185-192
Electronic Edition (link) BibTeX
Logic Built-In Self-Test
- Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Planar High Performance Ring Generators.
193-198
Electronic Edition (link) BibTeX
- Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel:
Logic BIST Using Constrained Scan Cells.
199-205
Electronic Edition (link) BibTeX
- Salvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
BIST Technique by Equally Spaced Test Vector Sequences.
206-216
Electronic Edition (link) BibTeX
Analog Testing I
Memory Testing II
- Baosheng Wang, Josh Yang, James Cicalo, André Ivanov, Yervant Zorian:
Reducing Embedded SRAM Test Time under Redundancy Constraints.
237-242
Electronic Edition (link) BibTeX
- Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk:
Memory BIST Using ESP.
243-248
Electronic Edition (link) BibTeX
- Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian:
A Methodology for Design and Evaluation of Redundancy Allocation Algorithms.
249-260
Electronic Edition (link) BibTeX
Analog Testing II
Defect Analysis and Fault Simulation
Issues in Reliability
Wireless and System Testing
System-on-Chip Testing
Analog Testing and Design Validation
Copyright © Sat May 16 23:47:01 2009
by Michael Ley (ley@uni-trier.de)
